Overview
DIGITAL-JU is a Coordination and Support Action under the Digital Europe Programme funding a continent-wide Chip Design Skills Programme with an indicative EU budget of €15 million and expected grant per project between €1,000,000 and €15,000,000. The call requires at least 60% of the project budget to be dedicated to hands-on student tape-out experiences via multi-project wafers, targets at least 1,000 students completing funded tape-outs within four years, and specifies a minimum project duration of five years. Single-stage proposals must be submitted electronically via the EU Funding & Tenders Portal by 24 September 2026 at 17:00 Brussels time and applicants must follow the Chips JU Guide for Applicants, include required ownership control declarations, and form appropriate consortia to deliver continent-scale training and MPW coordination.
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Highlights
What it funds
Scope and outcome
A Chips JU Coordination and Support Action to establish a comprehensive Chip Design Skills Programme across Europe. Focus on lowering barriers to entry to chip design and supporting multi-project wafer tape-outs as hands-on teaching. Expected outcomes include integration of practical chip design at multiple education levels, at least 1,000 students completing funded tape-outs over 4 years, stronger reskilling pathways and a sustainable Europe-wide chip design talent pipeline.
Hands-on requirement:At least 60% of the project budget must be dedicated to hands-on tape-out experiences (multi-project wafers) for university and secondary school students 1.
Who can apply
Consortia of organisations (e.g., universities, secondary schools, training providers, research organisations, industry partners, public bodies). Applicants must respect participation restrictions related to protection of digital infrastructure and complete Ownership Control Declarations as required by the call.
How to apply & procedure
Single-stage full proposal submitted via the EU Funding & Tenders Portal. Submission window opens 2026-07-07; deadline 24 September 2026. Use the Chips JU call page materials (application template and Guide for Applicants) for Part B layout and proposal limits.
- 1Type of action: Coordination and Support Action (CSA)
- 2Expected EU contribution per project: up to €15 000 000
- 3Mode: EU funding only; one expected grant
- 4Deadline: 24-09-2026 (single-stage)
| Budget item | Value |
|---|---|
| Expected grants | 1 |
| Minimum contribution (per proposal) | €1 000 000 |
| Maximum contribution (per grant) | €15 000 000 |
Contact and support:calls@chips-ju.europa.eu. Submit via the Funding & Tenders Portal entry for topic DIGITAL-JU Chips JU topic page.
Footnotes
- 1Call Guide and Application Form available from the Chips JU call page: Guide for Applicants - SCD.
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Breakdown
Call summary and objectives
Call identifier DIGITAL-JU. Title Stimulation of Chip Design. Type of action Coordination and Support Action (CSA). Single-stage full proposal. Submission deadline 24 September 2026. Planned opening date 7 July 2026. Expected EU contribution per project approximately €15 000 000. The call funds a comprehensive Chip Design Skills Programme to lower barriers to entry in chip design and tape-outs, with the explicit requirement that at least 60 percent of the budget supports hands-on tape-out experiences (via multi-project wafers) for university and secondary school students. Expected outcomes include practical chip design experience integrated into education at multiple levels, at least 1 000 students across Europe completing funded tape-outs over 4 years, stronger reskilling pathways for students from adjacent fields, and a sustainable continent-wide pipeline of chip design talent to support Europe's semiconductor ambitions.
Primary funding and budget:This topic is funded under the DIGITAL programme and managed via the Chips Joint Undertaking (Chips JU). Budget indicated in the portal: one expected grant, minimum contribution €1 000 000, maximum contribution €15 000 000 for 2026. The call documents confirm an expected EU contribution per project around €15 million. At least 60 percent of the requested budget must be allocated to hands-on tape-out experiences (multi-project wafers) for university and secondary school students.
Eligibility and applicant types
Eligible applicant types:the call is open to legal entities that can participate in EU grants under the Digital programme and Chips JU rules. Typical eligible entities include universities and other higher education institutions, research institutes, nonprofit organisations, industry partners including SMEs and large enterprises, training providers, public bodies and education authorities, vocational schools and secondary schools (participating as partners or beneficiaries), consortia of such organisations, and other relevant stakeholders in education and semiconductor ecosystems. The call is a Coordination and Support Action and therefore suits consortia that can organise and deliver large-scale training and student tape-out programmes across multiple countries. The call documentation references Consortium requirements including ownership control declarations and possible participation restrictions for protection of digital infrastructure; non-EU participants and special status participants are regulated by the general model grant agreement and specific call annexes.
Consortium, geographic scope and participation rules
Consortium requirement:consortium expected. The call is managed as a Coordination and Support Action and the portal indicates an open single-stage submission for one expected grant; the Guide for Applicants and call-specific templates describe consortium composition limits and required documents. The Chips JU call page states the programme seeks continent-wide implementation; beneficiaries must meet participation restrictions described in Annex 4 to the Chips JU Multiannual Work Programme and provide Ownership Control Declarations to support eligibility checks for protection of European digital infrastructures and supply chains. Beneficiary scope: EU Member States and other countries eligible to participate in the Digital programme and Chips JU activities as defined in the programme rules (EU and associated countries in the Digital/Chips JU framework). Proposals should follow the standard legal eligibility rules of the Digital programme and the Chips JU.
Mentioned countries and regions:The call text explicitly targets Europe and students across Europe; the managing bodies are EU-level (European Commission / Chips JU). Therefore the geographic scope is EU / Europe, and applicants should follow Chips JU eligibility and participation rules which apply to Member States and programme-associated countries. 1
Target sectors, technology and project stage
Target sector:semiconductors, microelectronics and chip design education. Thematic areas include digital technologies, semiconductor design workflows, tape-out processes, education and skills development, reskilling and workforce development for semiconductor ecosystems. Relevant technology areas: VLSI/ASIC design, mixed-signal and digital IC design methodologies, design for manufacturability, multi-project wafer integration, EDA tool chains, design verification, packaging awareness, and educational tooling and infrastructure to support student tape-outs. Expected project stage: education, training and hands-on demonstration; projects must deliver practical training, demonstrators and student tape-outs (so maturity ranges from education and training design through to demonstration and validation of student-produced chip designs).
Project outputs, targets and required commitments
Mandatory and recommended outputs:the call sets quantitative expectations — at least 1 000 students across Europe completing funded tape-outs over a 4 year period, integration of practical chip design into education at multiple levels (secondary and university), establishment of reskilling pathways, and creation of a sustainable, continent-wide pipeline of chip design talent. Financial allocation constraint: minimum 60 percent of the grant must be devoted to hands-on tape-out experiences through multi-project wafer runs or equivalent hands-on manufacturing engagement for students. Proposals must include operational plans for multi-project wafer (MPW) organisation, partner roles for education and fabrication coordination, quality assurance of student designs, curricula integration, outreach and reskilling pathways, and a sustainability plan for continuing talent pipeline after the grant period.
- 1Quantitative target: at least 1 000 students completing funded tape-outs within 4 years.
- 2Budget allocation: at least 60 percent allocated to hands-on tape-out experiences (MPW).
- 3Mandatory documents: Application form Part B (call-specific template), Guide for Applicants, Ownership Control Declaration (OCD) for each consortium member where applicable, and supporting annexes as listed in the call page.
- 4Participation restrictions: Annex 4 to the Chips JU Multiannual Work Programme applies; ownership control and infrastructure protection requirements must be met and declared.
- 5Timeframe: planned opening 7 July 2026, submission deadline 24 September 2026 (single-stage full proposal).
Funding modality and financial rules
Funding type:grant — specifically an EU budget-based Coordination and Support Action under the Digital programme and managed by Chips JU. The model grant agreement applicable is the Digital Europe Programme DEP MGA (budget-based) and the Chips JU specific annexes and rules. Funding form: budget-based action grant with standard eligible cost rules as set out in the DEP MGA template (personnel, subcontracting, purchases, other costs, indirect costs flat-rate 7 percent on eligible direct costs). Financial controls, reporting and audits follow the DEP MGA and Chips JU rules and the EU Financial Regulation 2024/2509. The maximum grant amount shown in the portal for this topic is €15 000 000. The call indicates one expected grant in the budget overview.
| Funding attribute | Details |
|---|---|
| Type of support | Grant, Coordination and Support Action (DIGITAL-JU-CSA) |
| Expected maximum contribution | Approx. €15 000 000 |
| Number of expected grants | 1 |
| Budget allocation constraint | At least 60 percent to hands-on tape-out experiences (multi-project wafers) |
| Eligible cost categories | Personnel, subcontracting, purchases (including MPW costs), travel, equipment (subject to MGA rules), other direct costs, financial support to third parties if applicable, indirect costs flat-rate 7 percent |
Application process and templates
Application type and submission:open one-stage call via the EU Funding & Tenders Portal. Applicants must use the Portal electronic submission system and the call-specific Part B application form template provided by Chips JU. The submission procedure is single-stage full proposal. Proposals must comply with the Part B layout and page limits described in the application form template and Guide for Applicants. The portal session for submission will be available from the planned opening date; once submission session is opened applicants can create draft proposals and upload required annexes. Applicants must ensure Ownership Control Declaration forms are included or submitted according to guidance in the call documentation when required.
Templates and required documents:Available and required templates include: Application form template Part B (call-specific), Guide for Applicants, Evaluation form, Ownership Control Declaration form template, DEP MGA and related model grant agreement documents, Rules for Legal Entity Validation and LEAR appointment, Chips JU work programme Appendices (Appendix 8 relevant), and Funding & Tenders Portal online manual. Applicants must follow the Part B structure (administrative Part A via portal and Part B narrative using the provided template). The call page provides links to all these documents and the Chips JU call page hosts the call-specific Guide for Applicants and Part B template.
Assessment, stages, success rates and co-funding
Application stages:Single-stage evaluation — applicants submit full proposals which are evaluated against published evaluation criteria using the call evaluation form. The portal indicates a single-stage submission procedure. Evaluation will follow the Guide for Applicants and the call-specific evaluation form template. Success rates: not specified in the call documents; typical success rates for Chips JU single-project CSAs vary by call and competition level. Applicants should assume competitive selection and address all evaluation criteria thoroughly. Co-funding requirement: standard EU CSA rules apply; the DEP MGA describes funding rates and eligible costs. The call documents and DEP MGA should be consulted for whether a co-funding percentage from beneficiaries is required; CSAs under Digital may fund a large share of eligible costs but applicants must follow the budget rules set out in the call and the MGA. No explicit co-funding percentage is stated in the call summary; refer to Guide for Applicants and Annex 2 of the MGA for funding rates and required co-financing rules if any.
- 1Application stages: 1 (single-stage full proposal).
- 2Submission method: EU Funding & Tenders Portal electronic submission only.
- 3Evaluation: independent experts using the published evaluation form; selection based on thresholds and ranking.
- 4Success rate: not provided in call documentation; expected to be competitive for a single multi-million euro grant.
Nature of support, permitted activities and third-party support
Nature of support:monetary grant funding (budget-based action grant) combined with non-monetary actions such as coordination, dissemination, networking and development of curricula. The call explicitly requires funds to be used for practical student tape-outs via multi-project wafer runs; this includes costs such as MPW mask sets, wafer runs, packaging and testing related to student designs, EDA tool access and training materials. Financial support to third parties: the DEP MGA allows financial support to third parties if declared in the call; the call documents list conditions for financial support to third parties and maximum per-recipient amounts where applicable. If proposes to use cascading grants or FSTP, applicants must follow the specific rules described in Annex 1, the Guide for Applicants and the DEP MGA.
Applicant requirements, responsibilities and compliance
Key applicant responsibilities include demonstrating administrative, financial and operational capacity to deliver a Europe-scale education and MPW programme; providing legal and financial entity validation (LEAR appointment), completion of Ownership Control Declarations where required, compliance with security and participation restrictions in Annex 4 of the Chips JU Multiannual Work Programme, and following DEP MGA contractual obligations including record-keeping, reporting, audits, IPR rules, visibility of EU funding and ethics/data protection rules. The coordinator role is accountable for consortium implementation, monitoring, reporting and distribution of payments. Consortium agreement is normally required and should address internal organisation, IP arrangements, payment distribution and liability among partners.
| Requirement | Description |
|---|---|
| Consortium agreement | Recommended/required by MGA; must clarify roles, access to results and payment distribution |
| Ownership Control Declaration | Required to assess ownership/control for digital infrastructure protection; forms to be uploaded per call guidance |
| Financial capacity checks | Standard EU financial capacity and legal entity validation apply (portal rules) |
| Reporting | Continuous reporting in Portal Continuous Reporting tool plus periodic technical and financial reporting per DEP MGA |
How to prepare a strong proposal — key technical and organisational points
Proposals should provide clear and detailed plans addressing curriculum integration across secondary and higher education, measurable targets to reach at least 1 000 students completing tape-outs within four years, a detailed budget allocating at least 60 percent to MPW and hands-on manufacturing costs, partnerships with EDA tool vendors, foundries or MPW aggregators, concrete reskilling pathways for students from adjacent fields, verification and testing workflows for student designs, quality assurance to ensure manufacturability and yield expectations, communication and dissemination plans, sustainability beyond the grant period (revenue or institutional adoption), and risk management including IP and export control considerations. Demonstrate operational experience in organising MPWs, managing student cohorts, and the capacity to coordinate continent-wide activities and collaborations with secondary schools, universities, vocational training centres and industry partners.
Quick checklist for applicants
- 1Confirm consortium composition and appoint coordinator; ensure all partners can meet legal entity validation and LEAR registration.
- 2Download and follow the call-specific Application Form Part B template and Guide for Applicants.
- 3Prepare Ownership Control Declarations where required and plan sensitive submission if needed.
- 4Design clear budget with at least 60 percent assigned to MPW and tape-out costs and justify all cost categories per DEP MGA rules.
- 5Detail educational integration, student recruitment and target numbers, MPW implementation plan, EDA tool access and foundry partnerships, and sustainability plan.
- 6Address ethics, data protection, and any security or participation restrictions described in Annex 4 of the Chips JU work programme.
- 7Plan for reporting, record-keeping and audits in line with DEP MGA and Digital programme rules.
Contact and support:for help related to this call contact calls@chips-ju.europa.eu. Portal and Chips JU call pages host the Guide for Applicants, Part B template, evaluation form and other call documents. Submission is via the EU Funding & Tenders Portal; applicant must follow portal instructions for creating and submitting the proposal and uploading annexes.
Long general summary
This Chips JU Coordination and Support Action funds a large-scale European Chip Design Skills Programme to build and sustain a pipeline of chip design talent. It targets education at secondary and university levels and supports hands-on student tape-outs via multi-project wafers. The initiative aims to deliver at least 1 000 student tape-outs in four years and to lower the barriers to chip design careers through curricula integration, reskilling pathways, practical tooling and manufacturing access. Applicants must form a consortium able to operate at continent scale, allocate at least 60 percent of the grant to hands-on tape-out experiences, and comply with DEP MGA financial and reporting rules and Chips JU participation and ownership control requirements. The call offers a single expected grant of up to around €15 million and is competitive; applicants should use the provided Part B template and Guide for Applicants, address all evaluation criteria, include Ownership Control Declarations where applicable, and prepare robust operational, educational and sustainability plans to ensure lasting impact on Europe's semiconductor skills ecosystem.
Footnotes
- 1Call page and official topic description: DIGITAL-JU — Stimulation of Chip Design. Official portal topic details and documents are available at the EU Funding & Tenders Portal: Call topic page.
Short Summary
Impact Create a sustainable, continent‑wide pipeline of chip design talent by integrating practical chip design experience into education and enabling at least 1,000 students across Europe to complete funded tape‑outs within four years. | Impact | Create a sustainable, continent‑wide pipeline of chip design talent by integrating practical chip design experience into education and enabling at least 1,000 students across Europe to complete funded tape‑outs within four years. |
Applicant Capacity to design and deliver large‑scale education and training programmes including organising multi‑project wafer (MPW) tape‑outs, managing EDA tool and foundry partnerships, running curricula integration and reskilling pathways, and handling operational, financial and reporting obligations under EU grant rules. | Applicant | Capacity to design and deliver large‑scale education and training programmes including organising multi‑project wafer (MPW) tape‑outs, managing EDA tool and foundry partnerships, running curricula integration and reskilling pathways, and handling operational, financial and reporting obligations under EU grant rules. |
Developments Hands‑on chip design education and workforce development focused on student tape‑outs via multi‑project wafers, VLSI/ASIC and mixed‑signal design workflows, design verification and manufacturability, EDA tool access, testing/packaging and reskilling pathways for adjacent disciplines. | Developments | Hands‑on chip design education and workforce development focused on student tape‑outs via multi‑project wafers, VLSI/ASIC and mixed‑signal design workflows, design verification and manufacturability, EDA tool access, testing/packaging and reskilling pathways for adjacent disciplines. |
Applicant Type Researchers, universities and other research organisations, SMEs/startups, large corporations, government organisations and NGOs/non‑profits active in education, training or semiconductor ecosystems. | Applicant Type | Researchers, universities and other research organisations, SMEs/startups, large corporations, government organisations and NGOs/non‑profits active in education, training or semiconductor ecosystems. |
Consortium Designed for multi‑partner consortia able to deliver continent‑scale training and MPW programmes (a consortium is expected). | Consortium | Designed for multi‑partner consortia able to deliver continent‑scale training and MPW programmes (a consortium is expected). |
Funding Amount Expected EU contribution per project between €1,000,000 and €15,000,000 (maximum ≈ €15,000,000; one expected grant within an indicative €15 million budget). | Funding Amount | Expected EU contribution per project between €1,000,000 and €15,000,000 (maximum ≈ €15,000,000; one expected grant within an indicative €15 million budget). |
Countries Targets EU Member States and eligible programme‑associated countries across Europe for continent‑wide implementation and student recruitment. | Countries | Targets EU Member States and eligible programme‑associated countries across Europe for continent‑wide implementation and student recruitment. |
Industry Digital Europe Programme managed by the Chips Joint Undertaking, targeting the semiconductor/microelectronics sector (skills and chip design capacity building). | Industry | Digital Europe Programme managed by the Chips Joint Undertaking, targeting the semiconductor/microelectronics sector (skills and chip design capacity building). |
Additional Web Data
Key Opportunity Details
Call Specifics
This Coordination and Support Action (CSA) under the Digital Europe Programme aims to strengthen chip design competencies in Europe by implementing a comprehensive Chip Design Skills Programme. The primary goal is to integrate practical chip design experience into education at multiple levels, targeting at least 1,000 students across Europe to complete funded tape-outs over a 4-year period 1.
Call Identifier:DIGITAL-JU
Type of Action:Coordination and Support Action (CSA)
Indicative EU Budget:€15 million (EU funding only) 2
Expected Grant per Project:Between €1,000,000 and €15,000,000 3
Funding Rate:100% of eligible costs 4
Deadline:24 September 2026 at 17:00 Brussels time 1
Project Duration:Minimum 5 years 1
Who Should Apply
Eligible applicants include universities, research institutions, and educational organizations capable of delivering a continent-wide Chip Design Skills Programme. The programme must support both university and secondary school students, with a mandatory requirement that at least 60% of the budget supports hands-on tape-out experiences via multi-project wafers 4.
Scope and Expected Outcomes
- 1Integration of practical chip design experience into education at multiple levels
- 2Completion of funded tape-outs by at least 1,000 students across Europe over 4 years
- 3Development of stronger reskilling pathways for students from adjacent fields
- 4Creation of a sustainable, continent-wide pipeline of chip design talent to support Europe's semiconductor ambitions
Budget Allocation Requirements
A critical condition of this call is that at least 60% of the total budget must be dedicated to hands-on tape-out experiences for students. This ensures that the programme prioritizes practical skills development over theoretical instruction 4.
Application and Submission Process
Proposals must be submitted electronically via the EU Funding & Tenders Portal. The submission procedure is single-stage. Applicants must ensure their proposal page limits and layout comply with Part B of the Application Form, available on the Chips JU website's Call page 5.
Official Portal:EU Funding & Tenders Portal
Helpdesk Contact:calls@chips-ju.europa.eu 5
Strategic Context
This call is part of the Chips Joint Undertaking's 2026 Skills-related Calls, designed to address the strategic challenge of talent shortages in the European semiconductor workforce. It aligns with the broader EU Chips Act objectives to double Europe's share of global semiconductor production from 10% to 20% by 2030 7.
Footnotes
- 1Chips JU 2026 Calls on Skills Info Session, SK Chips Competence Centre [[skchipscompetencecentre.sk
- 2EventsDetails - Chips JU, European Commission [[chips-ju.europa.eu
- 3Budget Overview from EU Funding & Tenders Portal for topic DIGITAL-JU
- 4New Chips JU calls under Digital Europe, NCP Flanders [[ncpflanders.be
- 5Topic Conditions and Support Info from EU Funding & Tenders Portal [[ec.europa.eu
- 6EU Chips Act, Optica [[optica.org
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