AI chip demonstrators for EU compute infrastructure

The call DIGITAL-JU under the Chips for Europe Initiative and the Digital Europe Programme funds PCB level demonstrators of AI chip prototypes designed by EU fabless companies and integrated with system partners. The topic budget is €10,000,000 for 2026 with an expected ten grants and individual EU contributions between €500,000 and €1,000,000. Selected demonstrators will be validated on a common EU evaluation platform and shortlisted solutions may receive an AI Compute Excellence label and progress to rack level development. Single stage full proposals must be submitted via the EU Funding and Tenders Portal by 23 September 2026 and enquiries can be sent to Calls@chips-ju.europa.eu.

Call identifier and type

DIGITAL-JU-CHIPS-2026-AI1-SG — DIGITAL JU Simple Grants

What it funds:PCB-level functional demonstrators of working AI chip prototypes designed by European fabless companies and physically integrated with system partners. Solutions will be validated on a common EU evaluation platform and a shortlist will be awarded the AI Compute Excellence label to progress to full rack development.

Who can apply:Primarily EU fabless chip designers in consortium with system partners (e.g., system integrators, test houses). Applicants must meet Chips JU participation and ownership-control rules; see call documents. Apply as a Simple Grant (single-stage).

1. 1Opening date: 2026-07-07; single-stage full proposal submission
2. 2Deadline: 2026-09-23 (UTC)
3. 3Mode: Co-funded with national funding authorities (NFA); subject to Chips JU restrictions

Essential documents and contact:Guide for applicants, Application Form template, Ownership Control Declaration and evaluation templates available on the Chips JU call page. For questions contact Calls@chips-ju.europa.eu. Full topic page: Chips JU topic page.

Call identification and timeline

Call title:DIGITAL-JU. Opportunity type: Call for Proposals (DIGITAL JU Simple Grants). Topic: AI chip demonstrators for EU compute infrastructure. Submission opening date: 2026-07-07. Submission deadline: 23 September 2026 (single-stage, full proposal). Mode: co-funded with national funding authorities (NFA) under the Chips Joint Undertaking (Chips JU) initiative. Call status: Open. Portal entry: ec.europa.eu.

Expected outcomes and purpose

This topic aims to fund demonstrators of working AI chip prototypes designed by European fabless companies and integrated with system partners, with validation performed on a common EU evaluation platform. The expected outcomes are: functional PCB-level AI chip demonstrators by EU fabless companies physically integrated with system partners; comparative validation evidence on key performance indicators via a common EU evaluation platform provided by the Topic X.B consortium; and a shortlist of European AI chip solutions awarded the AI Compute Excellence label and qualified to proceed to full rack development under Topic X.A2.

Funding, budget and number of expected grants

Indicative EU contribution per project:Approximately €1 000 000 per project. The call overview indicates expected grants: 10 projects; minimum contribution per grant: €500 000; maximum contribution per grant: €1 000 000; total topic budget for 2026: €10 000 000 ¹.

Who should apply and eligible applicant types

Primary eligible applicant types:EU fabless chip design companies (startups, scale-ups, SMEs, and potentially larger enterprises acting as lead beneficiaries), system integrator partners (SMEs or larger enterprises), research organisations and universities where relevant as partners, research and technology organisations (RTOs), non-profit entities and public bodies where they provide technical/system integration or evaluation support. The call is implemented as DIGITAL JU Simple Grants under the Digital programme; typical participants include private companies (startups, SMEs, large enterprises), universities, research institutes and non-profits. Associated partners, affiliated entities, subcontractors and third parties providing in-kind contributions can be involved as described in the template guidance and DEP MGA. Individual natural persons are not the target beneficiaries unless they are legal entities qualifying as natural person beneficiaries under the MGA rules.

Funding type and nature of support

Funding type:Grant (DIGITAL JU Simple Grant, budget-based action grant). Nature of support: monetary funding to beneficiaries (action grant budget-based) combined with access to non-monetary services: validation and evaluation on a common EU evaluation platform provided by Topic X.B consortium, lab/evaluation infrastructure, and potential labelling (AI Compute Excellence label) and selection for further funding under subsequent topics (Topic X.A2).

Consortium requirement and application mode

Consortium requirement:The call allows and anticipates multi-actor proposals that include fabless designers and system partners to physically integrate prototypes. The call documentation and the DEP MGA support both single-beneficiary (mono-beneficiary) and multi-beneficiary grants; however the topic description explicitly expects integration between chip designers and system partners, implying consortium proposals (fabless company + system partner(s)) are strongly recommended. Submission model: single-stage full proposal via the Funding & Tenders Portal (single-stage submission).

Beneficiary scope and geographic eligibility

Geographic eligibility:Applicants must be established in eligible countries defined by the JU and Digital programme rules. Primary target: EU Member States and possibly associated countries to the Digital Programme and Chips JU under the Programme 2021-2027. The call page indicates participation restrictions linked to protection of European digital infrastructures and supply chains; Ownership Control Declarations (OCD) must be completed by consortium members to assess eligibility and ownership/control aspects. Non-EU participants and international organisations may participate subject to specific conditions in the MGA and call documents, and may be subject to additional checks and pillar-assessment rules.

Target sectors and technical scope

Target sector:ICT and Semiconductor ecosystem, specifically AI accelerators and chips for infrastructure compute. Thematic areas include AI hardware, AI chips and systems, compute infrastructure integration, demonstrator design and validation, PCB-level prototyping, system integration, benchmarking and KPI validation on EU evaluation platform, and qualification for rack-level development. Cross-cutting priority: Digital agenda and Chips for Europe initiative.

Project maturity and expected project stage

Expected project stage:Technology readiness expected at prototype/hardware demonstrator level—working silicon prototypes assembled to PCB level and integrated with system partners for validation. This implies readiness at development/validation/demonstration TRL (advanced development ready for infrastructure integration), i.e. beyond idea and early research, with operational silicon available for immediate system-level validation.

Application process, templates and documentation

Application submission:Proposals must be submitted electronically via the EU Funding & Tenders Portal by the deadline. Applicants must use the Template of Application Form (Part B) specific to AI Simple Grants and follow the Guide for Applicants for DIGITAL-JU. Required documents and templates listed in the Topic Conditions: Template of Application Form, Template of Evaluation Form, Guide for Applicants, Chips JU Multiannual Work Programme, Annotated Model Grant Agreement (DEP MGA), Appendix 8 of the Work Programme, Ownership Control Declaration form template, National Budgets Table template, and call-specific Annexes and evaluation templates. Ownership Control Declarations should be prepared for all consortium members and merged into a single PDF for upload unless sensitive; an individual submission route for sensitive OCDs is provided.

Template structure and application form guidance:Applicants must complete Part A (administrative data) and Part B (technical proposal) using the provided Template of Application Form (Part B) AI SG. Part B contains sections with page limits and layout constraints described in Part B and Appendix 8 of the Chips JU Work Programme. The proposal must include a detailed technical description of the demonstrator, work plan and tasks, consortium composition and roles (fabricant/fabless, system integrator, test/validation partner), risk management, exploitation and dissemination plan, compliance statements including OCD, legal entity validation details, budget breakdown per beneficiary and budget category, and justification of costs. The proposal must respect the page limits for Part B set in the template and follow the evaluation criteria structure provided in the Template of Evaluation Form. Supporting Excel templates (National Budgets Table) and ownership control declaration Word template are provided. Continuous Reporting and Portal templates will be used if the proposal is selected.

Eligibility, selection and evaluation

Admissibility and eligibility:Proposals must comply with page limits and layout, legal entity validation and LEAR appointment, financial capacity and ownership control requirements. Participation restrictions apply to protect European digital infrastructures; applicants must complete Ownership Control Declarations. Evaluation: Proposals will be evaluated against the criteria set in the Template of Evaluation Form provided for the call. The Chips JU decision on evaluation and selection procedures applies. Selected demonstrators will be validated on the common EU evaluation platform and may be awarded the AI Compute Excellence label and shortlisted for Topic X.A2 full rack development. For technical and administrative queries applicants should contact Calls@chips-ju.europa.eu.

Budget categories, funding rules and cost eligibility

Grant form:budget-based action grant under the DEP MGA. Eligible cost categories follow the DEP MGA: personnel, subcontracting, purchases (travel, equipment, other goods and services), other costs (financial support to third parties if allowed), and indirect costs reimbursed at a flat-rate (7% of eligible direct costs A-D except volunteers and exempted categories). Equipment treatment follows DEP MGA rules (depreciation principle is default; call may specify exceptions). VAT rules and country restrictions apply as per the MGA and call conditions. Co-funding: the call is co-funded with national funding authorities; applicants should consult the Guide for Applicants and national co-funding rules in the Chips JU call page. Maximum grant amounts and funding rates per beneficiary will be specified in Annex 2 and possibly Annex 2e where complex funding rates apply.

1. 1Estimated number of grants: 10
2. 2Minimum EU contribution per grant: €500 000
3. 3Maximum EU contribution per grant: €1 000 000
4. 4Total topic budget for 2026: €10 000 000
5. 5Indirect costs flat-rate: 7% of eligible direct costs (categories A-D except specified exclusions)

Application stages, success rates and selection pipeline

Application stages:single-stage submission (one-stage full proposal). Evaluation and selection is managed by Chips JU using the published evaluation template and procedures. After award, selected demonstrators will undergo validation on the EU evaluation platform and may be shortlisted for the AI Compute Excellence label and subsequent activities (Topic X.A2). Success rates: not explicitly published for this call; estimated acceptance: up to 10 expected grants against an undefined number of applicants, so success rate will depend on number of valid applicants. Historically, similar competitive JU calls have single-digit to low double-digit percent success rates; applicants should assume moderate to high competition and prepare strong technical and integration evidence.

Co-funding and financial conditions

Co-funding requirement:The call is co-funded with national funding authorities (mode: co-funded with the NFA). Applicants must ensure national co-funding eligibility and follow national budgets table and co-funding mechanisms. The DEP MGA and call documentation specify rules for prefinancing, reporting, certificates and recovery, and may include requirements for financial guarantees depending on participant type. The Data Sheet indicates budgets and prefinancing/payment schedules will follow standard DEP MGA rules; certificates on financial statements may be required at final payment above threshold amounts.

Consortium composition and partners

Recommended consortium composition:a lead beneficiary (typically the fabless company designing the AI chip), at least one system partner responsible for physical integration and system-level validation, and optional partners: hardware test labs, research institutes or universities (for algorithm/system co-design, benchmarking), and the Topic X.B consortium (evaluation platform) as external validation provider. Roles and responsibilities should be clearly defined in Annex 1 of the application form and the consortium agreement. Ownership Control Declaration completion is required for all consortium members to assess participation restrictions.

Key requirements and technical expectations

Technical expectations include delivery of functional AI chip prototypes at PCB level, demonstrable integration with system partners (power, cooling, networking and software stack as relevant), validation on common EU evaluation platform with comparative KPI evidence, readiness for subsequent rack-level development for shortlisted solutions, and compliance with security and data protection obligations in DEP MGA and Chips JU rules. Applicants must include clear test plans, KPI definitions and benchmarking methodology aligned with the Topic X.B evaluation platform.

How the evaluation and validation chain connects to next phases

Demonstrators validated on the Topic X.B evaluation platform will be compared on KPIs; a shortlist will receive the AI Compute Excellence label indicating qualification to proceed to Topic X.A2 for full rack development. The evaluation platform provides comparative evidence to inform selection for scaling and integration into EU compute infrastructure.

Administrative contacts and support

For call-specific questions contact Calls@chips-ju.europa.eu. Technical and submission support: Funding & Tenders Portal FAQ, Portal IT Helpdesk (for account and submission technical issues), and the Funding & Tenders Portal Online Manual. Guide for Applicants and templates are available on the Chips JU call page and Funding & Tenders Portal. Latest updates and Q&A are published on the topic page.

Mentioned countries

No specific Member States are individually named in the scraped content. Geographic scope refers to EU Member States and eligible associated countries to the Digital Programme and Chips JU. Participation restrictions apply with respect to protection of European digital infrastructures; applicants must complete Ownership Control Declarations to enable eligibility checks.

Success statistics and risk considerations

Success rates are not published for this topic. Applicants should assume a competitive call with up to 10 grants to be awarded against an unknown number of submissions. Risks for applicants include failure to demonstrate operational silicon and PCB-level integration, insufficient KPI benchmarking plans, missing or incomplete Ownership Control Declarations, failure to secure national co-funding where required, and non-compliance with MGA eligibility or security restrictions. To mitigate risks, applicants should prepare robust technical evidence (silicon availability, PCB prototypes), define clear integration and validation responsibilities, ensure OCD completion, and coordinate with national funding authorities early.

Templates and application form structure

Available templates and documents listed for applicants:Guide for applicants - DIGITAL-JU; Template of Application Form (Part B) AI_SG; Template of Evaluation Form AI_SG; Ownership Control Declaration form template; National Budgets Table template (Chips JU); Chips JU Multiannual Work Programme; Appendix 8 of Work Programme - Chips for Europe Initiative; Annotated Model Grant Agreement (DEP MGA) and Model Grant Agreements documents. Applicants must follow the Part B structure and page limits described in the Guide for Applicants and Template of Application Form.

1. 1Part A: Administrative data and ethics/security declarations
2. 2Part B: Scientific/technical excellence and project description (with defined page limits and layout)
3. 3Work packages and tasks, milestones and deliverables
4. 4Consortium and roles; Ownership Control Declaration upload
5. 5Budget breakdown per beneficiary and budget categories; National Budgets Table where applicable
6. 6Impact, exploitation, dissemination and communication plan
7. 7Risk management and contingency plans
8. 8KPIs and validation/benchmarking methodology aligned with Topic X.B evaluation platform

Co-funding and national funding authorities

The call is co-funded with national funding authorities (NFA). Applicants must check national co-funding rules and coordination mechanisms. The National Budgets Table template is provided for reporting national co-funding contributions. The Guide for Applicants describes the co-funding mechanisms and any formal requirements to obtain national co-funding in parallel with EU proposal submission. Ensure national funder expectations and timing align with the EU grant schedule.

Security, ownership and participation restrictions

This call is subject to participation restrictions aimed at protecting European digital infrastructures, communications and information systems and related supply chains. Applicants must submit Ownership Control Declarations for each consortium member to allow ownership and control assessments. The OCD forms are provided and may be merged into a single PDF for the proposal upload or submitted individually in case of sensitive content. Failure to provide required OCD documentation may render a proposal ineligible.

Application timeline and practical steps

1. 1Register organisation and LEAR in the Participant Register and set up EU Login and roles.
2. 2Download and study Guide for Applicants and Template of Application Form (Part B).
3. 3Prepare technical proposal documentation including PCB-level demonstrator evidence, integration plans, KPI and benchmarking methods, consortium agreements and OCDs.
4. 4Prepare budget breakdown using the Template and National Budgets Table for co-funding entries.
5. 5Upload full proposal and supporting documents to the Funding & Tenders Portal before 23 September 2026.
6. 6Respond to any Topic Q&A clarifications published on the call page; contact Calls@chips-ju.europa.eu for specific queries.

Co-funding requirement: detailed description

Describe it:The call is explicitly co-funded with national funding authorities. Applicants must secure and document co-funding commitments from national sources where applicable. The National Budgets Table must be completed and submitted as part of the proposal. The EU contribution shown in the call is indicative and may be complemented by national contributions determined per project. The DEP MGA terms apply for financial management, reporting, certificates and recoveries. Applicants should consult national funders early to obtain co-funding confirmations and to align reporting and audit requirements between EU and national funds.

Success tips and recommended proposal content

Applicants are recommended to:provide concrete evidence of functioning silicon (photos, test results, wafer/packaging status), demonstrate PCB-level prototypes and system integration readiness, include clear KPI definitions and benchmarking methodology compatible with the Topic X.B evaluation platform, show collaboration agreements with system partners and test labs, provide realistic budgets and risk mitigation, prepare OCDs and legal/financial validation documents in advance, and align with national co-funding requirements. Use the provided templates and follow page limits strictly.

Final summary: what this opportunity is about

This call finances PCB-level demonstrators of AI chips designed by European fabless companies and integrated with system partners, supporting EU strategic autonomy in AI compute hardware. It provides monetary grants (approx. €0.5–€1.0Mper project) combined with access to a shared EU evaluation platform for comparative KPI validation and the possibility to be awarded an AI Compute Excellence label. The initiative is part of the Chips JU Chips for Europe initiative under the Digital Programme, is co-funded with national funding authorities, and is highly targeted at developers with operational silicon and system integration capability. Applicants must comply with DEP MGA rules, the Chips JU Guide for Applicants, complete Ownership Control Declarations, and follow the single-stage submission process. Successful demonstrators will be shortlisted for further rack-level development funding and integration into EU compute infrastructure.

Key contact:Calls@chips-ju.europa.eu. Submission portal: EU Funding & Tenders Portal topic page and submission entry-point. Read the Guide for Applicants and all call documents carefully and prepare ownership, legal and co-funding documentation early.

Reference and source:Chips JU call page and EU Funding & Tenders Portal topic details for DIGITAL-JU. For template downloads and official rules consult the call documents linked on the Chips JU website and the Funding & Tenders Portal.

This summary reproduces details provided on the official call pages and the DEP MGA documentation; applicants must consult the official call text and templates for binding information.

Footnotes

1. 1Budget overview information and expected grant counts are taken from the Funding & Tenders Portal topic data and the Chips JU call page: expectedGrants 10; minContribution €500 000; maxContribution €1 000 000; budgetYear €2026 10 000 000.

Call Details and Deadlines

This opportunity is part of the Chips for Europe Initiative under the Digital Europe Programme, specifically targeting the development of functional AI chip demonstrators. The call identifier is DIGITAL-JU, and the submission deadline is set for 23 September 2026 [[1]][[8]]. The call officially opened on 7 July 2026, with a single-stage submission procedure [[1]].

Expected Outcomes and Scope

The primary expected outcomes include functional demonstrators of working AI chip prototypes at the PCB-level, designed by EU fabless companies and physically integrated with their system partners [[1]]. Additionally, the project aims to validate AI chip solutions on a common EU evaluation platform to deliver comparative evidence on key performance indicators, ultimately creating a shortlist of European AI chip solutions awarded the 'AI Compute Excellence' label [[1]].

Funding Range and Budget:The total budget for this topic is €10,000,000 for 2026, with an expected number of 10 grants. The minimum contribution per grant is €500,000, and the maximum contribution is €1,000,000 [[1]].

Who Should Apply and Eligibility

This call is specifically designed for EU fabless companies that design AI chips, requiring them to collaborate with system partners for physical integration [[1]]. Applicants must be established in participating states of the Chips JU programme. The action type is 'DIGITAL JU Simple Grants', indicating a budget-based grant model [[1]].

Key Eligibility Highlights

1. 1EU fabless companies designing AI chip prototypes
2. 2Physical integration with system partners (PCB-level demonstrators)
3. 3Participation in validation on the common EU evaluation platform
4. 4Compliance with Chips JU participating state requirements

Application Process and Support

Proposals must be submitted electronically via the EU Funding & Tenders Portal. An information session was held on 3 July 2026 to present policy context, objectives, and practical guidance on eligibility and proposal preparation [[1]][[4]]. For specific questions regarding this call, applicants can contact the Chips JU office at calls@chips-ju.europa.eu [[1]].

Next Steps:Applicants should prepare their consortium including fabless designers and system partners, review the Guide for Applicants and Application Form templates available on the Chips JU website, and submit their proposal before the 23 September 2026 deadline [[1]].

Footnotes

1. 1Official call details and documents are available at the EU Funding & Tenders Portal: DIGITAL-JU-CHIPS-2026-AI1-SG.
2. 2Information session details and registration can be found on the Chips JU Events page: Info Session for AI Chips Calls.