International collaboration EU and Japan on semiconductors

Call DIGITAL-JU is a co-funded EU–Japan transnational call under the Chips for Europe Initiative, opening 7 July 2026 and closing 24 September 2026, to be submitted via the EU Funding & Tenders Portal. Indicative EU contribution is €3–€5 millionper project with an expected two grants and requires EU consortia to collaborate with Japanese partners under national co-funding arrangements. Projects must target TRL 5–7 and focus on advanced heterogeneous integration (2.5D/3D packaging), integrated photonics and standardised chiplet interfaces with demonstrations in laboratory and pilot manufacturing environments and clear industrial impact and knowledge transfer activities.

Call DIGITAL-JU-CHIPS-2026-SG-JAPAN — short summary

Essentials

Funds collaborative projects between EU consortia and Japanese partners to accelerate a chiplet ecosystem for AI and advanced process technologies beyond 2 nm. Projects must focus on heterogeneous integration (2.5D/3D packaging, integrated photonics), standardised chiplet interfaces, demonstration in lab and pilot environments and verification in semiconductor manufacturing use cases. Targeted Technology Readiness Levels: 5 to 7.

Who can apply:Consortia of eligible organisations established in the EU (industry, research organisations, SMEs, etc.) cooperating with Japanese consortia as described in the call conditions; applicants must follow participation restrictions and ownership control declaration requirements in Appendix 8. Apply via the Funding & Tenders Portal Topic page. ¹

1. 1Call type: DIGITAL JU Simple Grants (single-stage, full proposal).
2. 2Deadline: 24 September 2026 (submission open from 7 July 2026).
3. 3Budget per project: expected EU contribution about €3 000 000 to €5 000 000; call expects to fund around 2 grants (co-funded with national funding authorities).
4. 4Expected impact: immediate industrial relevance for European semiconductor manufacturing and industry uptake; knowledge transfer via workshops, publications and networking.

Proposals must demonstrate solutions across laboratory and pilot environments with verification in semiconductor manufacturing use cases and include stakeholder engagement activities. Follow application rules and templates in Appendix 8 of the Work Programme and the call-specific Guide for Applicants.

Footnotes

1. 1Full call text, application templates and Guide for Applicants are on the call page of the EU Funding & Tenders Portal Topic page.

Call basics and administrative information

Call identifier:DIGITAL-JU. Call type: Call for proposals — DIGITAL JU Simple Grants (Simple Grant — SG). Submission model: single-stage, full proposal (one-stage Full Proposal (FPP)). Opening date: 2026-07-07. Deadline / closing date: 24 September 2026 (2026-09-24T00:00:00+00:00). Mode: Co-funded with the National Funding Agency (NFA) in Japan (international co-funded call). Submission portal: EU Funding & Tenders Portal Funding & Tenders Portal. Contact for the call: Calls@chips-ju.europa.eu.

Expected EU contribution per project:Indicative EU contribution: approximately €3 000 000 to €5 000 000 per project. The Budget Overview for the topic indicates expected grants 2 and per-project minContribution 3 000 000 and maxContribution 5 000 000 for 2026 ¹.

Scope, objectives and expected outcomes

Aim:to support international collaboration between European and Japanese consortia focused on advanced semiconductor technologies and chiplet ecosystems. The call concentrates on technology areas that directly support AI functionality and future node process technologies beyond 2 nm through collaborative projects with Japanese partners and co-funding from Japan.

1. 1Primary technical targets: advanced heterogeneous integration (2.5D and 3D packaging), integrated photonics, and standardised chiplet interfaces enabling chiplet interoperability and a dynamic chiplet ecosystem.
2. 2Expected industrial impact: solutions must have direct and immediate impact on European industry, with verification in semiconductor manufacturing use cases.
3. 3TRL focus: the centre of gravity of envisaged work should address Technology Readiness Levels 5 to 7 (validation in relevant/pilot environments and manufacturing verification).
4. 4Demonstration requirement: projects must demonstrate solutions across laboratory and pilot environments and show verification in semiconductor manufacturing use cases.
5. 5Knowledge transfer and stakeholder engagement: proposals must include activities for knowledge transfer and stakeholder engagement such as industry workshops, publications and networking events.

Eligible applicants and consortium arrangements

General eligibility:this is a collaborative international call under the Chips for Europe Initiative. Applicants eligible to participate typically include industrial actors and research organisations that can deliver TRL 5-7 demonstrations and manufacturing verification. The call is subject to participation restrictions for protection of European digital infrastructure and supply chains; Ownership Control Declarations (OCD) are required for consortium assessment as described in the specific call documentation.

1. 1Eligible applicant types: SMEs, large enterprises, startups, universities, research institutes, public research organisations, non-profit research organisations, technology centres, consortia including industry and academia, and other legal entities that meet the call participation rules. Public bodies and EU-funded entities may participate following detailed rules in the call and MGA.
2. 2Consortium requirement: Consortium projects with EU participants and coordinated collaboration with Japanese consortia are expected; the topic targets international collaboration (EU-Japan). The call promotes co-funded projects with Japanese partners; therefore multi-actor consortium proposals are expected rather than single-entity submissions.
3. 3Beneficiary geographic scope: EU participants (EU Member States) and entities eligible to receive Chips JU funding; collaboration with Japanese consortia is supported via co-funding by Japanese NFA. Non-EU participants (Japan) participate under the co-funded modality; specific rules for non-EU participants apply (see Model Grant Agreement and Appendix 8).
4. 4Participation restrictions: the call is subject to specific participation restrictions described in Annex 4 to the Chips JU Multiannual Work Programme (protection of European digital infrastructures and supply chains). Ownership Control Declaration (OCD) must be provided for each consortium member and merged into one PDF when possible or submitted individually if sensitive.

Project characteristics, expected maturity and sectoral focus

Targeted project maturity and activities:Projects should target TRL 5 to 7, focusing on development, validation and demonstration activities with pilot runs and manufacturing verification. Emphasis is on heterogeneous integration and chiplet interoperability for AI, integrated photonics, and advanced process technologies beyond 2 nm.

1. 1Target sector(s): semiconductors, microelectronics, integrated photonics, advanced packaging (2.5D/3D), AI hardware enabling technologies, chiplet ecosystems, semiconductor manufacturing and process development beyond 2 nm.
2. 2Project stage: development, validation and demonstration (TRL 5-7).
3. 3Expected deliverables and outputs: technical demonstrators validated in laboratory and pilot manufacturing environments, standardised chiplet interface specifications or prototypes, integration of photonics for AI, documentation of manufacturing verification, dissemination outputs (workshops, publications) and stakeholder engagement events.

Funding modality, co-funding and budget details

Primary funding type:grant (DIGITAL JU Simple Grants under the Digital Programme / Chips JU model grant agreement framework). Mode: budget-based action grant (DIGITAL Action Grant Budget-Based). The call is co-funded with Japan (NFA), meaning projects will receive EU grant funding combined with national co-funding from Japan for the Japanese participants or coordinated budgets.

Application process, templates and submission

Submission route:single-stage Full Proposal submitted via the EU Funding & Tenders Portal submission system. Applicants must select the correct type of action and Model Grant Agreement (DIGITAL-AG) when creating their draft submission. Proposal page limits and layout are described in Part B of the Application Form in the submission system and in Appendix 8 of the Work Programme - Chips for Europe Initiative. Applicants can access the electronic submission service through the Portal. Support materials and templates specific to this call are provided on the Chips JU call page and Portal.

1. 1Available templates and call documents: Guide for Applicants DEP SG JAPAN; Template of Application_Form (Part B) SG JAPAN; Appendix 8 of Work Programme - Chips for Europe Initiative; Ownership Control Declaration form template; National Budgets Table template (xls); Annotated Model Grant Agreement for EU Funding Programmes 2021-2027; DEP MGA document for DIGITAL programme.
2. 2Proposal structure / templates: follow the Part B Application Form template for SG JAPAN (the Part B template defines page limits, required sections for technical description, impact and implementation, and budget tables). The Application Form (Part B) and supporting annexes must be uploaded in the Portal. Ownership Control Declarations from all consortium members should be merged into a single PDF (or submitted individually if containing sensitive data).
3. 3Submission guidance: use the Portal Online Manual and call-specific Guide for Applicants. The submission session for DIGITAL-JU is available in the Portal as of 2026-07-07.

Key submission links:Call topic page: Topic details . Chips JU call page and documents: Chips JU Call Details . Model Grant Agreement: DEP MGA.

Application eligibility and compliance details

Specific conditions and compliance requirements:proposals must respect the restrictions and declarations described in Appendix 8 of the Work Programme - Chips for Europe Initiative. Participation restrictions for protection of European digital infrastructures require completion of Ownership Control Declarations (OCD). Page limits and layout are set by the Part B template in the submission system. Applicants must ensure legal entity validation, LEAR appointment and compliance with financial capacity and ownership control assessments as required by the Chips JU and EU grants procedures.

1. 1Security and ownership controls: Annex 4 to the Multiannual Work Programme defines participation restrictions; applicants must provide OCDs for each consortium member.
2. 2Templates and declarations: use the Ownership Control Declaration form template and the National Budgets Table when preparing the proposal.
3. 3Ethics, confidentiality and data protection: proposals must follow ethical standards and data protection rules as described in the DEP MGA and call annexes.

Project implementation, reporting and funding rules

If selected for funding, projects will be implemented under the DIGITAL Action Grant Budget-Based model and the DEP MGA (Digital Europe Programme Model Grant Agreement). Standard rules on eligible costs, reporting cycles, continuous reporting via the Portal, record keeping, audits and final reporting apply. Indirect costs are reimbursed at the flat rate indicated in the DIGTAL MGA (standard 7% of eligible direct costs, unless modified in the specific grant agreement). Financial statements, certificates and audits follow the rules in the MGA and Data Sheet. Payments are made in euro and subject to the payment and recovery provisions of the MGA.

Application assessment, stages, co-funding and success rate

Application type:open competitive single-stage call (full proposals evaluated once). Evaluation and selection procedures follow Chips JU rules and the DEP MGA. The call documentation states expected grants: 2, with per-project EU contribution of €3-€5M. The call is co-funded by the Japanese NFA, therefore funded projects will have corresponding Japanese-funded activities in the joint consortia. Detailed evaluation criteria, scoring and thresholds are provided in the Guide for Applicants and the call-specific Part B template.

1. 1Application stages: single-stage evaluation (one submission stage).
2. 2Success rates: not published for this specific call; success rates will depend on the number and quality of submitted proposals. The call indicates an indicative expected number of grants (2) and the available EU budget envelope for the topic (indicative maximum contribution mapped at €5 000 000 in budget map).
3. 3Co-funding requirement: yes. This is an explicitly co-funded call with Japan's NFA. EU grant covers the EU contribution; Japanese participants will be covered by Japanese co-funding under national rules. Applicants must structure budgets and consortium roles to reflect co-funding arrangement and provide the National Budgets Table and OCD as required.

Templates and application form structure

Available and required templates:the call page provides a set of call-specific documents and templates. Key templates include the Part B Application Form (SG JAPAN) which defines the required sections and page limits; the Guide for Applicants DEP SG JAPAN; Ownership Control Declaration template; National Budgets Table; and Chips JU-specific annexes including Appendix 8 of the Work Programme - Chips for Europe Initiative. Applicants must follow the Part B template and the submission system guidance for page limits and formatting.

1. 1Recommended Part B structure (as per the Part B template and Guide for Applicants): Consortium description and roles; Excellence and technical approach (objectives, methodology, technical work packages addressing heterogeneous integration, chiplet interfaces, integrated photonics and AI support); Demonstration and validation plan across lab and pilot/manufacturing environments mapped to TRL 5-7; Exploitation and industrial impact plan showing direct and immediate impact on European industry; Knowledge transfer and stakeholder engagement activities (training, workshops, publications, networking events); Detailed work plan, milestones and deliverables; Risk management and contingency; Budget breakdown, including EU and Japanese co-funding contributions and National Budgets Table.
2. 2Ownership Control Declaration: one OCD per consortium member required to assess participation restrictions; merge into a single PDF where possible or submit individually if containing sensitive data.
3. 3National Budgets Table: required to present national co-funding contributions and split for the co-funded modality.

Explicitly mentioned countries and geographic detail

Explicit countries:Japan is explicitly referenced as the international partner and co-funder (NFA). Geographic eligibility: EU participants (EU Member States and entities eligible for Chips JU funding). The call is an EU-Japan international collaboration; Japanese consortia participate under co-funding arrangements.

Success factors and evaluation expectations

Evaluation emphasis will be on:technical excellence in heterogeneous integration and integrated photonics for AI, the maturity and realism of TRL 5-7 demonstrations, clear manufacturing verification plans and industrial relevance to European value chains, feasibility of standardised chiplet interface proposals and their interoperability potential, credible consortium with complementary capabilities (EU and Japanese partners), realistic workplan and budget, and strong knowledge transfer and stakeholder engagement commitments (workshops, publications, networking).

Quick reference timeline and budget table

Practical next steps for applicants

1. 1Review the call documents on the Chips JU call page and the Topic page on the EU Funding & Tenders Portal. Download Guide for Applicants, Part B template (SG JAPAN), Appendix 8 and OCD template.
2. 2Assemble a consortium with EU partners covering packaging, photonics, chiplet standards, manufacturing pilot capability and a Japanese partner consortium with committed national funding (NFA). Ensure legal entities can provide Ownership Control Declarations and meet participation restrictions.
3. 3Prepare the Part B technical description aligned to TRL 5-7 demonstration, include manufacturing verification work packages, define deliverables, milestones and stakeholder engagement activities.
4. 4Prepare the budget including EU requested amount (3-€5M) and indicate national co-funding for Japanese partners in the National Budgets Table. Ensure financial and legal validation steps (LEAR, entity validation) are in place.
5. 5Submit the full proposal via the EU Funding & Tenders Portal before 2026-09-24 and keep records of the digitally signed submitted proposal.

For help related to this call contact Calls@chips-ju.europa.eu. For submission technical issues use the Portal IT Helpdesk and the Funding & Tenders Portal Online Manual.

Success rate:Success rates for this specific call are not published. The call indicates an indicative number of expected grants (2) and an EU budget per project mapping. Applicants should assume competitive selection and structure proposals to maximise industrial impact and cross-border collaboration.

Detailed answers to categorisation questions

1. 1Eligible Applicant Types: Broad range including SMEs, startups, large enterprises, universities, research institutes, public research organisations, non-profit research organisations, technology centres and other legal entities able to implement TRL5-7 semiconductor integration, photonics and packaging demonstrations. Consortiums must include EU participants; Japanese consortia participate under national co-funding arrangements.
2. 2Funding Type: Grant (DIGITAL JU Simple Grants — budget-based action grants under the Digital Programme / Chips JU).
3. 3Consortium Requirement: Consortium (multi-partner collaborative projects expected). The call targets EU-Japan collaborative consortia; single-beneficiary mono-grant is not the intended modality.
4. 4Beneficiary Scope (Geographic Eligibility): EU participants eligible for Chips JU funding plus Japanese partners via co-funding from Japan's NFA. The primary funding for EU partners is EU (Chips JU); Japanese partners are funded via NFA co-funding arrangements.
5. 5Target Sector: Semiconductors / microelectronics, integrated photonics, advanced packaging (2.5D and 3D), chiplet ecosystems, AI hardware enabling technologies, semiconductor manufacturing and advanced process nodes beyond 2 nm.
6. 6Mentioned Countries: Japan is explicitly mentioned. The geographic region for funded beneficiaries is the EU (European Union) for EU grant contribution; collaboration with Japan is built into the call modality.
7. 7Project Stage: TRL 5-7 (development, validation and demonstration; pilot manufacturing verification).
8. 8Funding Amount: Indicative EU funding per project €3 000 000 to €5 000 000. Budget map shows expectedGrants 2 and budgetYearMap 2026: €5 000 000 (topic-level maximum indicated).
9. 9Application Type: Open call, single-stage Full Proposal (one-stage FPP) submitted through the EU Funding & Tenders Portal. Co-funded with NFA — requires coordination with Japanese partners and national co-funding arrangements.
10. 10Nature of Support: Monetary support (grants) to beneficiaries; additionally non-monetary support via network, workshops and dissemination activities is expected as part of project activities.
11. 11Application Stages: 1 (single-stage evaluation; full proposal submission then evaluation and selection).
12. 12Success Rates: Not specified. Indicative number of grants: 2. Final success rate depends on number and quality of proposals.
13. 13Co-funding Requirement: Yes. The call is explicitly co-funded with the Japanese NFA. EU grant covers EU contribution; Japanese partners obtain national funding through NFA. Applicants must present budgets and National Budgets Table reflecting co-funding.

Concluding summary

This Chips JU call DIGITAL-JU solicits collaborative EU-Japan proposals to advance semiconductor technologies critical for AI and next-generation nodes beyond 2 nm. Projects should focus on advanced heterogeneous integration (2.5D/3D packaging) and integrated photonics, and the development and validation of standardised chiplet interfaces to foster an interoperable chiplet ecosystem. Proposals must address TRL 5-7 activities, demonstrate laboratory-to-pilot manufacturing verification with immediate and direct impact on European industry, and include strong knowledge transfer and stakeholder engagement. The call is a single-stage open call with indicative EU contributions of €3–€5Mper project and expected two grants. It is co-funded with the Japanese National Funding Agency, requires careful alignment of EU and Japanese budgets and documentation (including Ownership Control Declarations), and follows the DIGITAL DEP Model Grant Agreement and Chips JU Work Programme rules. Applicants should use the Part B template and Guide for Applicants provided, include National Budgets Table and OCDs, assemble an EU-Japan consortium with manufacturing and integration capabilities, and prepare a robust TRL5-7 demonstration plan with clear industrial exploitation and dissemination activities.

Footnotes

1. 1Budget overview and topic budget mapping referenced from the EU Funding & Tenders Portal topic entry indicating expected grants (2) and per-project min and max contribution €3 000 000 to €5 000 000 for 2026. See the topic page Topic details and Chips JU call page Chips JU Call Details.

Call Details and Timeline

This call, titled DIGITAL-JU, is a joint transnational funding opportunity under the Chips for Europe Initiative to strengthen collaboration between Europe and Japan on next-generation semiconductor technologies for AI [[1]][[2]]. The call opened on 7 July 2026 and closes on 24 September 2026 at 00:00 UTC [[1]][[2]].

Key Dates:Opening: 7 July 2026; Deadline: 24 September 2026 [[1]][[2]].

Funding Amounts and Budget

The EU budget for this topic is €5,000,000, with an expected number of 2 grants awarded [[1]]. Each grant has a minimum contribution of €3,000,000 and a maximum contribution of €5,000,000 [[1]]. National co-funding is available in participating countries, such as Denmark (up to €650,000 per partner or €1.3M if coordinator) and Sweden (€10 millionSEK) [[1]][[2]].

Scope and Expected Outcomes

Projects must focus on advanced heterogeneous integration, particularly in 2.5D and 3D packaging and integrated photonics to support AI functionalities [[1]][[2]]. Key outcomes include developing standardized chiplet interfaces for interoperability and fostering a dynamic chiplet ecosystem [[1]]. Solutions must be demonstrated across laboratory and pilot environments with verification in semiconductor manufacturing use cases [[1]].

Technology Readiness Level (TRL):The centre of gravity of the work must address TRL 5-7 (laboratory to pilot environment) [[1]][[2]].

Eligible Applicants and Consortium Requirements

1. 1EU-based organizations in Chips JU participating states
2. 2Japanese organizations (strong collaborative links required)
3. 3Cross-sector partnerships (industry, academia, research)

Additional Requirements and Knowledge Transfer

Proposals must facilitate knowledge transfer and promote stakeholder engagement through industry workshops, publications, and networking events [[1]]. Projects should engage material scientists, chemical engineers, semiconductor manufacturers, and AI experts to bridge research and industrial applications [[1]]. Expected outcomes must have direct and immediate impact on European industry [[1]].

For support related to this call, contact Calls@chips-ju.europa.eu [[1]].

Footnotes

1. 1Official call details and scope are available at the EU Funding & Tenders Portal EU Portal.