IA Resilience call reinforcing Europe's strenght in power electronics

This Innovation Action HORIZON-JU supports projects to reinforce Europe’s power electronics value chain, prioritising Wide Bandgap substrates and 300 mm GaN/SiC platforms, advanced packaging and heterogeneous integration, device-level intelligence and AI-enabled system approaches. The topic has an indicative budget of €20 million and is expected to fund two projects with an approximate EU contribution of €10 million per project (range €1M–€10M). Submission is single-stage via the EU Funding & Tenders Portal with a deadline of 16 September 2026 and targets TRL 5–8 with industrial demonstration and scale-up. Eligible consortia must comprise multiple legal entities from Horizon-eligible countries and comply with Chips JU participation rules, including Ownership Control Declarations and security-related participation restrictions.

Call HORIZON-JU-CHIPS-2026-FT1-IA (Innovation Action)

High-level summary

Purpose:fund innovation projects that strengthen Europe's power-electronics value chain, focusing on wide bandgap substrates and platforms (GaN/SiC at 300 mm), advanced packaging and integration, novel device concepts, AI-enabled system-level improvements, advanced characterisation, and technologies to increase voltage/frequency/current/thermal performance and supply stability.

Who can apply:Consortia of organisations eligible to participate in Chips JU innovation actions (applicants must follow Chips JU call rules, submit required templates and Ownership Control Declarations where requested) ¹.

Funding scale:Expected EU contribution per project approximately €10 000 000; topic budget indicative: €20 000 000 (expected grants: 2). Individual project contributions in the topic range from €1 000 000 to €10 000 000.

1. 1Technology areas funded: WBG substrates and 300 mm GaN/SiC platforms, UWBG and tooling for device innovation, packaging/integration solutions, heterogeneous integration, advanced characterisation, AI at system level.
2. 2Action type: HORIZON JU Innovation Action (single-stage submission).
3. 3Administrative requirements: use Chips JU templates and application forms; follow legal entity validation and ownership control requirements.

Apply and find call documents on the official topic page Call topic details.

Footnotes

1. 1See the Chips JU Guide for Applicants and Appendix 7 to the Multiannual Work Programme for eligibility, required templates (application Part B, ownership-control declarations) and evaluation rules: Chips JU call documents.

Call summary and scope

Essential facts

Call identifier HORIZON-JU. Type of action:HORIZON JU Innovation Actions (IA). Single-stage submission. Submission deadline: 16 September 2026 (call opened 7 July 2026). Expected EU contribution per successful project approximately €10 000 000. Overall 2026 budget allocated to the topic: €20 000 000 with expected 2 grants. Submission and management take place via the Funding & Tenders Portal; submission entry points and the model grant agreement selection are available in the portal. For help contact calls@chips-ju.europa.eu.

Scope:The call is a resilience-oriented Innovation Action to reinforce Europe's strength in power electronics across multiple technology domains. Proposals should address one or more of the following domains: WBG substrates to reduce EU material dependency and provide sustainable industrially compatible solutions; WBG platform cost-effectiveness at 300 mm for GaN and/or SiC to improve yield and power density and close value-chain gaps; development of a toolbox including wafer cut, smart stacking, thin layer transfer, epitaxy, UWBG materials for further innovation schemes; next-generation or optimised new power semiconductor devices tailored to their application; adding intelligence to power semiconductor devices on control and/or sensor side; propagation of EU packaging and integration excellence across the value chain including pre-packages and packaging solutions to enable device/system integration; exploration of heterogeneous and functional integration to improve performance, reliability, robustness and cost competitiveness; tackling rising operative voltage, frequency, current and thermal challenges common across application sectors; providing stable and clean power supply to minimise disruptions and data corruption; advanced characterisation techniques for new materials, devices and systems; and implementation of AI at system level and/or use of AI methods to accelerate innovation.

Target technological activities and innovations:Proposals may include but are not limited to: wide bandgap substrates and epitaxy (GaN, SiC, UWBG), 300 mm wafer platforms for GaN and/or SiC, advanced packaging and pre-package solutions, heterogeneous integration approaches, novel device architectures and materials, smart stacking and thin layer transfer techniques, wafer cut technologies, device-level sensors and embedded intelligence, AI-driven system-level design and process optimisation, and advanced characterisation and metrology methods for materials, devices and integrated systems.

Eligibility and application details

Eligible applicant types

Eligible applicants are legal entities that can participate in Horizon/EU grants and Chips JU calls. Typical participating organisation types expected and eligible: SMEs, startups, large enterprises (industry and manufacturing), universities, research institutes, public research organisations, non-profit organisations, technology transfer organisations, hospitals and clinical actors if relevant for demonstrators, National/Regional public authorities where applicable, and public-private partnerships or consortia combining these types. Individual natural persons are not eligible as sole applicants. Projects are expected to be implemented by consortium partners with complementary competences.

Consortium requirement

The topic is designed for multi-partner Innovation Actions. Proposals should be submitted by consortia. The Funding & Tenders Portal indicates a single-stage submission for Innovation Actions; the Chips JU call page refers to consortium submissions and requires Ownership Control Declarations for each consortium member as part of eligibility and security-related participation restrictions. The call documentation and Appendix 7 to the Chips JU Work Programme give full details on participation rules and required consortium documentation.

Beneficiary geographic eligibility

Primary beneficiaries must meet Horizon/Chips JU participation rules. This typically includes entities established in EU Member States, Horizon Associated Countries, and other countries explicitly eligible under the Horizon Europe / Chips JU rules. The call is managed by the Chips JU and is focused on reinforcing European capabilities, so eligible participants are primarily EU/Associated country legal entities. Specific participation restrictions for protection of European digital infrastructures and supply chains apply and are described in Annex 4 of the Chips JU Multiannual Work Programme; participants must complete Ownership Control Declarations where required.

Target sectors

Primary thematic sectors targeted by the call:power electronics, electronic components and systems, semiconductor manufacturing (power semiconductor devices), advanced packaging and integration, wide bandgap semiconductor technologies (GaN, SiC, UWBG), advanced materials and substrates, AI for hardware and system design, characterization and metrology, clean and stable power systems across multiple application sectors (energy, transport, industrial, data centres). Cross-cutting digital agenda priorities such as AI and digitisation are explicitly mentioned.

Mentioned countries

No specific countries are named in the topic text. The topic is targeted at European actors and follows Horizon/Chips JU eligibility rules, i.e., entities established in the EU and Horizon-associated countries are the primary intended applicants.

Project maturity and expected stage

Expected project stage:development, validation, demonstration and scale-up readiness. The topic is an Innovation Action focused on scaling to 300 mm production and strengthening value chain resilience, implying TRL range around TRL 5 to TRL 8 (from pilot lines and demonstration through pre-commercial scaling). Proposals should demonstrate industrial relevance and a path to industrial deployment.

Funding amount and budget

Budget overview for the topic in 2026:planned topic budget €20 000 000. Expected grants: 2. Minimum contribution per project indicated in portal metadata: €1 000 000. Maximum contribution per project indicated: €10 000 000. The Chips JU call page highlights expected EU contribution per project approximately €10 000 000.

Funding mechanism:Primary financial mechanism: grant under the Horizon Action Grant Budget-Based model grant agreement (HORIZON-AG). The call uses the HORIZON JU Innovation Actions modality.

Application process and templates

Submission is single-stage via the European Commission Funding & Tenders Portal. Applicants must select the correct action and model grant agreement at submission. The portal provides the Electronic Submission Service. Draft proposals previously started are available in My Proposals after login. Required supporting documents and templates are provided on the Chips JU call page and in the call documents section.

1. 1Mandatory forms and templates supplied by Chips JU: Template Application form Part B IA-RIA-FT FPP (Part B application template), 2026 Guide for Applicants RIA_IA_FT-FPP, Evaluation Form Chips IA RIA FT-FPP, Ownership Control Declaration form template, National Budgets Table template (xls), Chips JU Multiannual Work Programme and Appendix 7 (Electronic Components and Systems), Annotated Model Grant Agreement for EU Funding Programmes 2021-2027, Rules for legal entity validation, LEAR appointment, financial capacity and ownership control assessment.
2. 2Security/participation restrictions: Annex 4 of the Multiannual Work Programme imposes participation restrictions to protect digital infrastructures and supply chains. Ownership Control Declarations (OCD) must be completed by each consortium member and merged into a single PDF for upload with the proposal. Where OCDs contain sensitive data, participants may submit them individually via a provided form.
3. 3Submission guidance: Use the Submission button next to the chosen type of action and MGA on the Funding & Tenders Portal; confirm selection when prompted; consult the Funding & Tenders Portal Online Manual and FAQs for technical submission issues; contact Funding & Tenders Portal IT Helpdesk for login/access problems.

Application type, stages, success rate and co-funding

Application type:open competitive call with a single-stage submission process through the Funding & Tenders Portal. Number of evaluation/selection stages: single-stage submission followed by evaluation and selection (effectively one submission-evaluation decision). The portal and call documents refer to evaluation and selection procedures established by the Chips JU and to the evaluation form for IAs; the process includes administrative checks, eligibility, and scoring against evaluation criteria as set out in the Guide for Applicants and the Evaluation Form. Success rate: the call indicates two expected grants from a topic budget of €20 000 000. The exact success rate cannot be determined from the topic text alone because it depends on the number of eligible proposals submitted; given limited expected grants, the call will be highly competitive. Co-funding: the grant will follow the rules set in the Annotated Model Grant Agreement and the Guide for Applicants. Innovation Actions typically require co-financing of eligible costs (the EU contribution does not cover 100 percent of total costs); applicants must follow the applicable reimbursement rates and co-financing rules outlined in the Guide for Applicants and the Model Grant Agreement. Applicants should consult the Guide for Applicants and the MGA for the exact applicable reimbursement rates and eligible cost rules.

Nature of support and eligible output types

Nature of support:monetary grants (direct financial contribution) to support research and innovation activities under an Innovation Action. Support may also be complemented by non-financial services available through Chips JU and the European ecosystem (partner search, project coaching, access to networks), but the primary modality is grant funding. Expected outputs: development and demonstration of power electronic devices and platforms, pilot 300 mm lines or demonstrators, advanced packaging solutions and pre-packages, design tools and AI-enabled system solutions, characterization and metrology results, roadmaps for industrial deployment and supply-chain strengthening, and exploitation/uptake plans.

Evaluation, restrictions and supporting documents

Evaluation:Proposals will be evaluated using the Chips JU Evaluation Form for IAs/RIA FPP and the criteria described in the Guide for Applicants and the Multiannual Work Programme appendices. The call is subject to specific participation restrictions aimed at protecting European digital infrastructures, communications and information systems, and related supply chains. Applicants must complete Ownership Control Declarations for each consortium member as described in the call documentation. Legal entity validation, LEAR appointment and financial capacity checks will apply according to the Chips JU rules and the Annotated Model Grant Agreement.

Templates, guidance and contact points

1. 1Core documents provided on the Chips JU call page and Funding & Tenders Portal: 2026 Guide for Applicants RIA_IA_FT-FPP, Template Application Form Part B IA-RIA-FT FPP, Evaluation Form Chips IA RIA FT-FPP, Ownership Control Declaration form template, National Budgets Table template, Chips JU Multiannual Work Programme (Appendix 7 Electronic Components and Systems), Annotated Model Grant Agreement, Rules for legal entity validation, LEAR appointment and financial capacity assessment.
2. 2Submission technical guidance: Funding & Tenders Portal Online Manual and Portal FAQs; Funding & Tenders Portal IT Helpdesk for access and technical submission support.
3. 3Call-specific contact: calls@chips-ju.europa.eu for questions specific to the topic; include the call topic identifier in correspondence.

Applicants must consult and use the provided Part B template and the Guide for Applicants for proposal structure, page limits, evaluation criteria and requested Annexes. Specific instructions on ownership control, security-related participation restrictions and required declarations are in the Multiannual Work Programme Appendix 7 and the Ownership Control Declaration template. The portal requires the correct selection of the model grant agreement at submission and will not permit changing this choice after confirmation.

Risk, competitiveness and strategic considerations

This call is explicitly resilience-focused and aims to reduce European dependencies in the power electronics value chain by targeting upstream materials (WBG substrates), wafer-scale manufacturing at 300 mm, packaging and integration, device intelligence, heterogeneous integration and scale-up to industrial-relevant manufacturing. Proposals should present strong industrial involvement, credible exploitation and deployment plans, clear contributions to supply-chain resilience, and alignment with the ECS Strategic Research and Innovation Agenda and Chips JU Multiannual Work Programme. Given the small number of expected grants, evaluated proposals should demonstrate high impact, clear TRL progression to industrial deployment, feasible workplans, risk mitigation, and appropriate consortium coverage of the full value chain.

Applicants should carefully address ownership control, legal entity validation and security participation restrictions early in proposal preparation to avoid eligibility problems at submission and to comply with Chips JU requirements.

Success rate and competition:The exact success rate cannot be calculated from published call data because it depends on the number of eligible applications submitted. The topic indicates two expected awards; therefore, competition is expected to be high and selection will prioritise proposals with strong industrial scaling potential, clear path to 300 mm deployment and demonstrable impact on EU resilience in power electronics.

How to prepare a competitive submission

1. 1Form a consortium that covers the full value chain from materials and epitaxy through device design, packaging, integration and end-user demonstrators; include industrial partners able to lead scale-up and exploitation.
2. 2Demonstrate TRL progression and clear pilot or demonstrator plans at industrially relevant scale (300 mm readiness where applicable), with credible cost and timeline estimates.
3. 3Address supply-chain resilience impact, material sourcing strategies and how proposed solutions reduce EU dependencies.
4. 4Include clear exploitation, business and scale-up plans, and describe how results will be industrialised in Europe.
5. 5Provide Ownership Control Declarations for all consortium members and ensure compliance with participation restrictions described in the Multiannual Work Programme Annex 4.
6. 6Use the exact Part B template and follow page limits, structure and evaluation criteria in the Guide for Applicants; supply all requested annexes and the National Budgets Table where relevant.

Further resources and official links:applicants should download and read the call-specific documents on the Chips JU call page and the Funding & Tenders Portal. Full templates and evaluation forms are provided by the Chips JU and must be used. For submission technical support use the Funding & Tenders Portal Online Manual and IT Helpdesk; for call content questions contact calls@chips-ju.europa.eu.

Footnote and official guidance:Applicants must consult the 2026 Guide for Applicants, the Template Application form Part B IA-RIA-FT FPP, the Annotated Model Grant Agreement and Appendix 7 to the Chips JU Work Programme for full instructions and rules on eligibility, evaluation, financial conditions and ownership control requirements ¹.

Overall summary

This Chips JU Innovation Action call HORIZON-JU is a resilience-focused funding opportunity to reinforce Europe's strength in power electronics. It seeks multi-partner Innovation Actions that can combine materials innovation (WBG substrates, epitaxy), wafer platform scaling to 300 mm for GaN and/or SiC, device innovation, advanced packaging and heterogeneous integration, AI-enabled system-level approaches, and advanced characterisation to accelerate industrial deployment and close value-chain gaps. The call is single-stage, competitive, and expects to fund approximately two projects at around €10 million each from a €20 million allocation. Applicants should prepare consortia spanning research and industry, follow the provided Part B template and Guide for Applicants, address Ownership Control Declaration and participation restrictions, and demonstrate a clear path to industrial-scale demonstration and exploitation in Europe.

Footnotes

1. 1Key call documents and templates are available on the Chips JU call page and the Funding & Tenders Portal: 2026 Guide for Applicants RIA_IA_FT-FPP; Template Application form Part B IA-RIA-FT FPP; Ownership Control Declaration form template; Appendix 7 to the Chips JU Multiannual Work Programme - Electronic Components and Systems; Annotated Model Grant Agreement; Evaluation Form Chips IA RIA FT-FPP. Contact calls@chips-ju.europa.eu for call-specific queries.

Call Overview and Strategic Objectives

This Innovation Action (IA) aims to scale Europe's power electronics manufacturing to 300mm device production and adopt agile design, directly addressing EU dependency on non-EU suppliers and strengthening technological sovereignty [[3]]. The call targets the industrialization of next-generation power semiconductor technologies, focusing on Wide Bandgap (WBG) substrates like GaN and SiC to improve yield, power density, and energy efficiency [[2]].

Key Funding Details

Scope and Innovation Domains

Proposals must address one or more of the following domains to reinforce the European power electronics ecosystem [[3]].

1. 1Developing Wide Bandgap (WBG) substrates to reduce material dependency and provide sustainable, industrially compatible solutions.
2. 2Creating cost-effective WBG platforms available in 300mm for GaN and/or SiC to improve yield and close value chain gaps.
3. 3Developing enabling toolboxes including wafer cutting, smart stacking, thin-layer transfer, epitaxy, and Ultra-Wide Bandgap (UWBG) materials.
4. 4Designing next-generation or optimized power semiconductor devices tailored for specific industrial applications.
5. 5Integrating intelligence, sensing, and control capabilities directly into power semiconductor devices.
6. 6Advancing EU excellence in packaging and integration, including pre-packages and power module solutions for system integration.
7. 7Exploring heterogeneous and functional integration to enhance performance, reliability, robustness, and cost competitiveness.
8. 8Developing advanced characterization techniques for new materials, devices, and systems.
9. 9Implementing AI at the system level or using AI methods to accelerate innovation speed.

Eligibility and Consortium Requirements

The call is open to a diverse range of organizations including SMEs, large enterprises, power semiconductor manufacturers, universities, research institutes, RTOs, equipment manufacturers, packaging companies, and system integrators [[3]].

Eligible Countries:Participation is limited to legal entities established in EU Member States, EEA countries (Iceland, Liechtenstein, Norway), Horizon Europe Associated Countries, OECD countries, Mercosur countries, and nations with Digital Partnership or Trade and Technology Council agreements with the EU [[3]].

Projects must involve collaboration across the complete European power electronics value chain, from materials and semiconductor technologies through packaging to end-use applications [[3]]. A consortium must typically include at least three independent legal entities from different eligible countries [[15]].

Participation Restrictions and Compliance

This call is subject to participation restrictions for the protection of European digital infrastructures, communication systems, and related supply chains [[3]]. Participants must submit Ownership Control Declarations (OCD) for all consortium members to assess eligibility regarding ownership control [[3]]. While optional for the Pre-Proposal (PO) phase, all OCDs must be merged into a single PDF and uploaded with the full proposal, unless sensitive data requires individual submission via the specific form [[3]].

Application Process and Support

Proposals are submitted via the EU Funding & Tenders Portal. The submission session opened on 7 July 2026 [[4]]. Applicants must follow the Part B layout detailed in the Application Form and refer to the 2026 Guide for Applicants RIA_IA_FT-FPP [[3]].

1. 1Download the 2026 Guide for Applicants RIA_IA_FT-FPP from the Chips JU Call page.
2. 2Prepare the Ownership Control Declaration (OCD) for all consortium members.
3. 3Ensure the consortium includes at least three entities from different eligible countries.
4. 4Submit the Full Project Proposal (FPP) before 16 September 2026, 17:00 Brussels time.
5. 5Contact calls@chips-ju.europa.eu for specific call-related questions [[3]].

Projects should build on existing European initiatives, collaborate with the Wide Bandgap (WBG) Pilot Line, and exploit synergies with other Chips Act pilot lines and Competence Centres [[3]].

Footnotes

1. 1Official call details and documents are available at the EU Funding & Tenders Portal EU Funding Portal.
2. 2The Chips JU Multiannual Work Programme 2023-2027 and Appendix 7 (ECS 2026) provide the strategic framework for this call Chips JU Work Programme.