DIGITAL-JU-CHIPS-2025-SG-SSOI

The EU grant opportunity titled DIGITAL-JU-CHIPS-2025-SG-SSOI is a part of the Digital Europe Programme, focusing on advancing silicon-on-insulator (sSOI) technology. The call is currently open, allowing submissions until November 20, 2025. The total budget for this initiative is €30 million, with grants ranging from €1 million to €30 million. The expected impact includes developing standard Process Design Kits (PDKs) to support the transition to 7nm FD-SOI technology, enhancing sSOI substrate production capabilities, and driving the creation of intellectual property within Europe.

Eligible applicants can include universities, research institutions, small and medium-sized enterprises (SMEs), large companies, and public-private partnerships involved in the semiconductor ecosystem. While the call emphasizes a collaborative approach, it suggests that forming a consortium may be required due to the project's industrial-scale goals. Geographic eligibility predominantly covers EU member states and associated countries.

The primary target sector is semiconductors, with a specific focus on advanced materials and manufacturing. The project stage is oriented towards development and scaling up sSOI substrates for industrial production. The application process is strictly a single-stage evaluation without pre-selection rounds.

The funding mechanism is a grant, covering up to 50% of total project costs, indicating that co-funding will be necessary from applicants or national sources. However, the call does not specify exact co-funding requirements. Various support types, including financial grants and skill development initiatives, are part of the offering.

To successfully apply for this grant, proposals must demonstrate comprehensive plans to develop industrial-grade sSOI substrates with low defect density and ensure compatibility with existing semiconductor manufacturing processes. The call seeks projects that enhance Europe’s capacity in semiconductor manufacturing and technological leadership.

Detailed information and conditions regarding the application process, including required documents, submission guidelines, evaluation criteria, and legal frameworks, are available on the Chips Joint Undertaking website and the EU Funding & Tenders Portal. Technical support and further clarifications can be sought via provided contact emails or the online help resources.

The DIGITAL-JU-CHIPS-2025-SG-SSOI call, part of the Digital Europe Programme (DIGITAL), aims to create a sustainable accelerator accessible to all European stakeholders, providing access to state-of-the-art sSOI (strained silicon-on-insulator) technology and manufacturing capabilities. This is a DIGITAL JU Simple Grant, utilizing a DIGITAL Action Grant Budget-Based model agreement. The call is currently open for submission with a single-stage deadline.

The opening date for submissions is July 8, 2025, and the deadline for submission is November 20, 2025, at 17:00:00 Brussels time. The total budget allocated to this topic is 30,000,000 EUR. The expected contribution per grant ranges from 1,000,000 to 30,000,000 EUR, with an indicative number of 1 grant to be awarded.

The expected impact of this call includes:

Developing and standardizing Process Design Kits (PDKs) based on validated sSOI substrate data. These PDKs should enable designers to optimize system-level architectures and support the transition to 7nm FD-SOI (fully depleted silicon-on-insulator) technology, ensuring readiness for high-volume manufacturing by 2030.

Expanding the capabilities of sSOI substrates to industrial-scale wafer production, focusing on achieving low defect densities and improved manufacturing yields that meet the standards of advanced semiconductor fabrication.

Driving the creation of intellectual property and strengthening Europe's production capacity in sSOI technologies, contributing to Europe's leadership in critical semiconductor markets.

Fostering collaborative development through synergies with other Chips JU pilot lines, with a particular focus on complementarity with the FD-SOI pilot line, enhancing the overall innovation capacity and technological leadership of Europe in semiconductor technologies.

Providing comprehensive training programs and skill development initiatives to equip European technologists and engineers with the expertise necessary for sSOI substrate integration and advanced semiconductor manufacturing.

The scope of the call requires the proposed accelerator to address all levels of key technological steps required to bring sSOI substrates to industrial scale. This includes:

Development of industrial-grade sSOI substrates, focusing on achieving low defect density, crucial for enhancing electron mobility and ensuring high-performance FD-SOI devices at the 7 nm node. This involves refining strain engineering techniques, particularly to introduce a uniform global strain that can balance the performance for strained NMOS (n-type metal-oxide-semiconductor) and relaxed PMOS (p-type metal-oxide-semiconductor) transistors.

Ensuring compatibility with existing semiconductor manufacturing by refining process integration and optimization. This includes improving epitaxial growth, wafer bonding, and defect reduction techniques to meet the requirements of advanced FD-SOI production processes.

Promoting collaboration across the semiconductor ecosystem, working with other pilot lines, and connecting to the design platform and competence centers.

The admissibility conditions include proposal page limits, layout, and annexes, which are described in the Calls documents section on the Chips JU Call page and in Appendix 6-v4 of the Chips JU Workprogramme.

Other conditions include: Eligible Countries, Other Eligible Conditions, Financial and operational capacity and exclusion, Evaluation and award: Submission and evaluation processes, Evaluation and award: Award criteria, scoring and thresholds, Evaluation and award: Indicative timeline for evaluation and grant agreement, and Legal and financial set-up of the grants. Detailed information on these conditions can be found on the Call page of the Chips JU Website.

The Call Documents Section contains all the necessary documents, including:

Reference documents: Guide for Applicants, Evaluation form.

Call submission documents and annexes: Application form template Part B, National funding table template, Ownership declaration template.

Additional documents: DEP Regulation 2021/964, EU Financial Regulation 2024/2509, Rules for Legal Entity Validation, LEAR Appointment and Financial Capacity Assessment, EU Grants AGA Annotated Model Grant Agreement, Funding & Tenders Portal Online Manual, Funding & Tenders Portal Terms and Conditions, Funding & Tenders Portal Privacy Statement.

To facilitate partner searches, LEARs, Account Administrators, and self-registrants can publish partner requests for open and forthcoming topics on the Funding & Tenders Portal.

To submit a proposal, applicants must access the Electronic Submission Service by clicking the submission button next to the relevant type of action and model grant agreement. Existing draft proposals can be accessed by logging into the Funding & Tenders Portal and selecting the My Proposals page.

For help related to this call, applicants can contact calls@chips-ju.europa.eu. Technical support is available through the Funding & Tenders Portal FAQ and the IT Helpdesk. The Online Manual provides a step-by-step guide through the Portal processes.

In summary, this EU grant opportunity aims to bolster Europe's semiconductor industry by creating a sustainable accelerator for sSOI technology. It focuses on improving manufacturing capabilities, fostering innovation, and enhancing collaboration within the semiconductor ecosystem. The grant supports projects that can develop and standardize PDKs, expand sSOI substrate production, drive IP creation, and provide training programs. The call is structured to ensure compatibility with existing manufacturing processes and to promote collaboration among various stakeholders, ultimately strengthening Europe's position in the global semiconductor market.

Eligible Applicant Types: The call is open to all European stakeholders. The specific types of eligible applicants are not explicitly mentioned in the provided text, but given the nature of the call, eligible applicants could include, but are not limited to, research organizations, universities, SMEs, large enterprises, and other entities involved in the semiconductor industry.

Funding Type: The funding type is a grant, specifically a DIGITAL JU Simple Grant, which falls under the DIGITAL Action Grant Budget-Based [DIGITAL-AG] model.

Consortium Requirement: The text does not explicitly state whether a single applicant or a consortium is required. However, the emphasis on collaboration across the semiconductor ecosystem and synergies with other Chips JU pilot lines suggests that consortia are encouraged.

Beneficiary Scope (Geographic Eligibility): The call is open to all European stakeholders, indicating that the geographic eligibility is focused on entities within Europe.

Target Sector: The target sector is semiconductor technology, specifically focusing on silicon-on-insulator (sSOI) technology and advanced semiconductor manufacturing.

Mentioned Countries: No specific countries are mentioned, but the focus is on European stakeholders, implying that entities from EU member states and potentially associated countries are eligible.

Project Stage: The project stage is focused on development and industrial scaling of sSOI substrates, implying a stage beyond basic research and towards demonstration and industrial readiness. The call aims to create a sustainable accelerator, suggesting a focus on scaling up existing technologies.

Funding Amount: The budget overview indicates a total budget of 30,000,000 EUR for the topic DIGITAL-JU-CHIPS-2025-SG-SSOI. The contributions per grant are expected to range from 1,000,000 EUR to 30,000,000 EUR.

Application Type: The application type is an open call, as indicated by the "Open For Submission" status. It is a single-stage submission process.

Nature of Support: The beneficiaries will receive money in the form of a grant.

Application Stages: The application process is a single-stage process.

Success Rates: The indicative number of grants is 1, given the budget and contribution ranges. This suggests a highly competitive call with a low success rate, likely below 10%.

Co-funding Requirement: The text does not explicitly mention a co-funding requirement.

Summary:

This is a DIGITAL JU Simple Grant call under the Digital Europe Programme, specifically targeting the advancement of silicon-on-insulator (sSOI) technology and manufacturing capabilities in Europe. The call, DIGITAL-JU-CHIPS-2025-SG-SSOI, aims to create a sustainable accelerator that provides access to state-of-the-art sSOI technology and manufacturing capabilities for all European stakeholders. The primary goals include developing and standardizing Process Design Kits (PDKs) to support the transition to 7nm FD-SOI technology by 2030, expanding sSOI substrate production to industrial scale with low defect densities and improved manufacturing yields, driving intellectual property creation, and strengthening Europe's production capacity in sSOI technologies.

The call emphasizes complementarity with the FD-SOI pilot line and collaboration with other Chips JU pilot lines to enhance innovation and technological leadership in semiconductor technologies. It also includes comprehensive training programs and skill development initiatives for European technologists and engineers.

The scope of the call covers all levels of key technological steps required to bring sSOI substrates to industrial scale, including the development of industrial-grade sSOI substrates with low defect density and compatibility with existing semiconductor manufacturing processes. This involves refining strain engineering techniques, improving epitaxial growth, wafer bonding, and defect reduction techniques.

The call is open for submission with a deadline of November 20, 2025. The total budget is 30,000,000 EUR, with individual grants ranging from 1,000,000 EUR to 30,000,000 EUR. The application process is a single-stage submission. Applicants are encouraged to collaborate across the semiconductor ecosystem, working with other pilot lines and connecting to design platforms and competence centers. The call aims to support projects that are beyond basic research and focused on demonstration and industrial readiness, with the goal of scaling up existing technologies.