Chiplet for Defence Application

The European Defence Fund (EDF) is offering a research grant titled "Chiplet for Defence Application EDF-2025-RA-MATCOMP-CDA-STEP," aimed at advancing chiplet technology with heterogeneous packaging for defence systems. This initiative focuses on enhancing the European Defence Technological and Industrial Base (EDTIB) and fostering innovation in deep and digital technologies in line with the Strategic Technologies for Europe Platform (STEP). The submission process is single-stage, with applications open from February 18, 2025, until October 16, 2025, at 17:00 Brussels time. The total budget allocated for this topic is €25 million.

Eligible applicants include consortia involving large enterprises, small and medium-sized enterprises (SMEs), and research institutions from EU Member States and EDF Associated Countries, with at least two independent entities required from different eligible countries. The funding takes the form of actual costs grants to cover project-related expenses. The primary focus is on research and development at an early stage, excluding system prototyping, testing, and certification activities.

The target sector revolves around defence applications, specifically related to semiconductors and advanced packaging technologies. Proposals are encouraged to explore the integration of different technologies (e.g., GaN, GaAs, and Si) into chiplet architectures for various defence needs such as radar, communications, and electronic warfare systems.

Proposals must demonstrate practical applications and are encouraged to analyze current architectures, generate knowledge on chiplet integration, and study feasibilities for military applications. Key considerations include cost efficiency, power consumption, scalability, and cybersecurity measures.

While specific success rates for this grant opportunity are not provided, competition typically results in lower success rates. Co-funding requirements remain unspecified in the current data. Proposals should be aligned with EU strategic autonomy goals and seek to develop a common hardware library of chiplets for military applications.

In conclusion, this grant provides a significant opportunity for collaboration among EU-based entities to innovate in the defence electronics field, particularly leveraging chiplet technology to create flexible and efficient systems that reduce dependency on non-European supply chains.

The European Defence Fund (EDF) is offering a research grant, EDF-2025-RA-MATCOMP-CDA-STEP, focused on "Chiplet for Defence Application". This initiative aims to explore and develop chiplet technology combined with heterogeneous packaging for defense systems, contributing to the Strategic Technologies for Europe Platform (STEP) objectives in deep and digital technologies. The call is for EDF Research Actions (EDF-RA) and utilizes an EDF Action Grant Budget-Based [EDF-AG] Model Grant Agreement. The submission model is single-stage, with the opening date for submissions being 18 February 2025 and a deadline of 16 October 2025, 17:00:00 Brussels time. The total budget allocated for this topic is 25,000,000 EUR.

The expected impact of this call is to develop and share a common hardware library of chiplet building blocks, identify EU-based building blocks compatible with advanced architectures for defence components, increase the competitive advantage of the European Defence Technological and Industrial Base (EDTIB) in component development and integration, and enhance the flexibility of architectures to create multifunctional systems adaptable to evolving capability needs.

The objective is to explore the potential of chiplet technology and heterogeneous packaging for defence applications. This involves combining chiplets made with different technologies such as GaN, GaAs, and Si, along with analogue, mixed analogue/digital, and digital functions, to achieve new processing power capabilities while maintaining reasonable cost and power consumption. The goal is to create new or improved devices for various defence applications, including radar, electronic warfare, communication, munition, and signal processing systems.

The scope of the call includes the development and sharing of a common hardware library of chiplets for military applications, requiring a thorough analysis of possible architectures and the design of at least one military application. Proposed architectures should prioritize EU-based technologies and consider existing EU manufacturing facilities and programs like Chips JU. Key considerations for the architecture include non-dependence for defence systems, cost efficiency for low volume quantities (including Non-Recurring Engineering costs), power consumption, scalability for adjusting System in Package (SiP) performances, and integration of security features (cybersecurity) to protect the resulting SiP.

Eligible activities under this topic include:

Activities that aim to create, underpin, and improve knowledge, products, and technologies, including disruptive technologies, which can achieve significant effects in the area of defence (generating knowledge) Yes (mandatory)

Activities that aim to increase interoperability and resilience, including secured production and exchange of data, to master critical defence technologies, to strengthen the security of supply or to enable the effective exploitation of results for defence products and technologies (integrating knowledge) Yes (mandatory)

Studies, such as feasibility studies to explore the feasibility of new or upgraded products, technologies, processes, services and solutions Yes (mandatory)

Design of a defence product, tangible or intangible component or technology as well as the definition of the technical specifications on which such design has been developed, including partial tests for risk reduction in an industrial or representative environment Yes (mandatory)

System prototyping of a defence product, tangible or intangible component or technology No

Testing of a defence product, tangible or intangible component or technology No

Qualification of a defence product, tangible or intangible component or technology No

Certification of a defence product, tangible or intangible component or technology No

Development of technologies or assets increasing efficiency across the life cycle of defence products and technologies No

Mandatory activities for proposals include:

Generating Knowledge:

Analysis of the current state of the art in different use-cases where chiplet-based architectures are implemented, such as processing, signal conversion, and mixed-signal applications.

Demonstration of the advantages of chiplet architectures for defence applications.

Identification of available chiplet and integration technologies inside and outside Europe, including a description of the supply chain for each technology and an estimation of technology benefits.

Integrating Knowledge:

Defining electronic functions of military systems that can or should be realized with a chiplet approach.

Identifying benefits and risks for defence based on available and needed technologies, including defining shortfalls and possible dependency risks for each technology.

Studies:

Exploring the feasibility of chiplet architecture for defence, including:

Defining which components-of-the-shelf can be used and which chiplets need to be developed, along with their required performances for a given feature.

Studying possible interface solutions between chiplets.

Identifying the best compromise between performance and sovereignty (security of supply), scalability (in memory, cells, number of processing cores), specialization (compute accelerator, specific RF front-end), security, and reliability.

Defining the possible supply chain, considering the use of EU foundries, especially for sensitive components, and the adequacy of the supply chain to the targeted volume.

Identifying cost drivers of the targeted architecture configuration.

Design:

Defining targeted performances, including expected functions and their technical specifications for at least one type of military application based on the chiplet approach.

Defining partial and risk reduction tests needed to validate the proposed design.

Proposed designs must:

Integrate multiple (at least two) chiplets using different technologies or nodes.

Be compatible with the studied supply-chain optimization.

Be compatible with the de-risking tests.

Evaluation of the final design in terms of performances and supply-chain optimization on a representative demonstrator.

Additional tasks that proposals should cover include:

Design:

Covering the scalability of the architecture (addition or reduction of the amount of chiplets of one single type in the architecture).

Optional tasks for proposals may include:

Design:

Designing more than one type of military application, with associated specifications, test definitions, design, and evaluation.

Addressing scalability of different features simultaneously (e.g., adding memory chiplets and processing cores for a given architecture), including specification, test definition, design, and evaluation.

Including security features.

Including features dedicated to the implementation of Artificial Intelligence in the system.

Software development for the evaluation of the demonstrator(s).

Proposals should substantiate synergies and complementarity with activities in advanced packaging and semiconductor nodes, such as those described in call topics EDF-2022-RA-MATCOMP-PACOMP, DIGITAL-JU-Chips-2023-SG-CPL-3, and DIGITAL-JU-Chips-2023-SG-CPL-2, as well as projects under the European Chips Act.

Functional requirements for proposed products and technologies include:

The interface between chiplets should be compatible with different types of military applications (standardization approach).

2.5D or 3D integration should be based on EU capacities.

Advanced packaging should be based on System-in-Package technology.

The design should optimize the power consumption of the system.

The proposed design should be compatible with operations in harsh environment conditions of the targeted application.

The design should be compliant with REACH and ROHS regulations.

The call document and annexes include:

Call document (available shortly)

Application form templates:

Standard application form (EDF) available in the Submission System

Detailed budget table (EDF RA)

Participant information (EDF)

List of infrastructure, facilities, assets, and resources (EDF)

Actual indirect cost methodology declaration (EDF)

Ownership control declaration

PRS declaration (EDF)

Model Grant Agreements (MGA):

EDF, ASAP, and EDIRPA MGA

Additional documents:

EDF Annual Work Programme

EDF Regulation 2021/697

EDF Programme Security Instruction (PSI)

EU Financial Regulation 2024/2509

Rules for Legal Entity Validation, LEAR Appointment, and Financial Capacity Assessment

EU Grants AGA Annotated Model Grant Agreement

Funding & Tenders Portal Online Manual

Funding & Tenders Portal Terms and Conditions

Funding & Tenders Portal Privacy Statement

For help related to this call, applicants can contact DEFIS-EDF-PROPOSALS@ec.europa.eu. Additional resources include EDF Info-days 2025, Funding & Tenders Portal FAQ, the IT Helpdesk, and the Online Manual.

In summary, this European Defence Fund call seeks to foster innovation in defence electronics by promoting the development and use of chiplet technology and heterogeneous packaging. It encourages collaboration among EU-based entities to create a common hardware library of chiplets, enhance the flexibility and scalability of defence systems, and reduce dependence on non-EU technologies. The call emphasizes cost efficiency, power consumption, security, and compliance with relevant regulations, aiming to bolster the competitiveness and resilience of the European defence industry.

Eligible Applicant Types: The eligible applicant types are not explicitly stated, but based on the nature of the call, eligible applicants likely include entities such as startups, SMEs, large enterprises, universities, research institutes, and other organizations capable of conducting research and development in the area of defence electronics and chiplet technology. The call emphasizes the use of EU-based technologies, suggesting a focus on applicants within the EU.

Funding Type: The funding type is a grant, specifically "EDF Research Actions implemented via actual cost grants (EDF-2025-RA)" and "EDF Action Grant Budget-Based [EDF-AG]".

Consortium Requirement: The opportunity requires a consortium, as it is indicated that "Union funding shall be granted following competitive calls for proposals. Participation in these calls is open to any consortium complying with the requirements".

Beneficiary Scope (Geographic Eligibility): The geographic eligibility is primarily focused on EU-based entities, as the call emphasizes the use of EU-based technologies and manufacturing facilities. Norway is also mentioned as an associated country.

Target Sector: The target sector is defence, specifically defence electronics, deep and digital technologies, advanced packaging, and advanced semiconductor nodes. It includes applications in radar systems, Electronic Warfare systems, communication systems, munition applications, and signal processing applications.

Mentioned Countries: The text mentions the EU and Norway explicitly.

Project Stage: The project stage is focused on research, design, and feasibility studies, with a Technology Readiness Level (TRL) of 6. The call excludes system prototyping, testing, qualification, and certification, indicating that the projects should be in the earlier stages of development.

Funding Amount: The funding amount varies depending on the specific topic within the call, ranging from €10 million to €39 million. For the specific topic EDF-2025-RA-MATCOMP-CDA-STEP, the budget is €25 million.

Application Type: The application type is an open call, with a single-stage submission process.

Nature of Support: The beneficiaries will receive money in the form of a grant to fund their research and development activities.

Application Stages: The application process involves a single stage.

Success Rates: The success rates are not explicitly mentioned in the provided text.

Co-funding Requirement: The text does not explicitly mention a co-funding requirement.

Summary:

This opportunity is a call for proposals under the European Defence Fund (EDF) for research actions focused on exploring and developing chiplet technology for defence applications. The call, titled "Chiplet for Defence Application," aims to foster the development of a common hardware library of chiplets, promote EU-based technologies, and enhance the capabilities of defence systems through heterogeneous packaging and innovative architectures.

The specific objective is to investigate how chiplet technology and heterogeneous packaging can improve defence systems, potentially leading to new capabilities in processing power, cost efficiency, and power consumption. The call encourages combining chiplets made with different technologies (GaN, GaAs, Si, etc.) and integrating analogue, mixed analogue/digital, and digital functions.

Eligible activities include generating knowledge through analysis and demonstration, integrating knowledge by defining electronic functions and identifying benefits and risks, conducting feasibility studies to explore chiplet architecture, and designing defence products with partial tests for risk reduction. System prototyping, testing, qualification, and certification activities are not eligible.

The scope of the call includes analyzing architectures, designing at least one military application, and using EU-based technologies where available. Proposals should address non-dependence, cost efficiency, power consumption, scalability, and cybersecurity. Synergies with other initiatives like the European Chips Act and related call topics are encouraged.

The call is a single-stage process with a deadline of October 16, 2025. The indicative budget for the EDF-2025-RA-MATCOMP-CDA-STEP topic is €25 million. The expected outcome is to develop a common hardware library of chiplets, identify EU-based building blocks, increase the competitive advantage of the European Defence Technological and Industrial Base (EDTIB), and enhance the flexibility of defence architectures.

In essence, this call seeks to advance the state-of-the-art in defence electronics by leveraging chiplet technology and heterogeneous packaging, with a strong emphasis on EU-based solutions and supply chains. It supports research, feasibility studies, and design activities aimed at creating more capable, cost-effective, and secure defence systems.